SPI disabling i2c and vice-versa on Developer Kit

No I haven’t. Could you provide some explanations of how I could do that?
Can I find the original file available for download somewhere? Or should I flash the original OS again and make a copy of this file?
Where is the dtb file located on the Xavier?

Thanks!

You can get it by Host that install the sdkmanager and check the UI to get the path to get original dtb at …/Linux_for_Tegra/rootfs/boot/

Hi! I’m not sure I really understand your last message.
I have flashed the “original” OS image downloaded from the Nvidia website with the intent to check if I can get both i2c and SPI to work again at the same time.
For now I have not yet enabled anything, just flashed the OS and booted the Xavier and did not touch the pins configuration.
I have found a whole bunch of dtb files in /boot.


If I want to go back to the original/vanilla pin configuration on my hardened OS, which files should I take from here to use as replacement on my hardened one?
Thanks!

To add again more information: I have now enabled SPI1 with jetson-io.py and rebooted to apply the changes.
After the reboot, my i2c device is still detected and working fine (that’s good) but the SPI still doesn’t work for some reason, despite being enabled (I checked again with jetson-io):


I get this error message when I try to read from my SPI device:

Traceback (most recent call last):
File “scripts/current2.py”, line 15, in
spi.open(bus, device)
FileNotFoundError: [Errno 2] No such file or directory

Is there something I forgot to do? (also my last message remains valid: if I get this to work again on this vanilla OS I will have to somehow carry those positive changes to my hardened OS).
Thanks!

You may need below command to enable the spidev driver

sudo modeprobe spidev

Yes, this did the trick!
So I now have my Xavier NX Dev Kit with the original OS with both my i2c and SPI working.
Which config files or dtb files should I then copy over to my hardened OS to get the same configuration?

Thanks!

Your current dtb should be generate by jetson-io. check the /boot/extlinux/extlinux.conf

This is the content of the file:


Do I understand correctly that I should copy the file /boot/kernel_tegra194-p3668-all-p3509-0000-user-custom.dtb onto my hardened OS and edit this line in the /boot/extlinux/extlinux.conf of my hardened OS to point to the file?

Thanks!

Don’t know what’s hardened OS.
If it’s another device then yes you can apply this dtb by that.

As explained in my very first message, I have to use a hardened Operating System for this application. This means that I used the default OS downloaded from the Nvidia website, and I then hardened it following the CIS-CAT guidelines for Ubuntu server level 1.
This involves changing permissions, removing non-used packages, setting up all kinds of security features.

So I have one SD card with my hardened OS loaded on it, which is the one that I need to get to work as it is the one I have to use in the end, and one SD card with the “default” OS. Thanks to your help it now works on the default OS (confirming that there is no hardware issue), but I need to get this to work on the hardened one.

Going back to my problem, I have now copied over the dtb file and edited the /boot/extlinux/extlinux.conf, and I have made sure that the ownership and group of the files are root, I have rebooted, and now I can read my i2c device but my SPI device gives me the No such file or directory error.
AIBOX11

I have tried sudo modprobe spidev of course but that has no effect, I still get the error.
This what my pin configuration now looks like:

Any idea what else could cause this issue now, where I can’t access SPI despite SPI being enabled and having ran modprobe spidev?

For information, below are the configuration-related items we had to comply to:

w Benchmark Item
1 Initial Setup
1.1 Filesystem Configuration
1.1.1 Disable unused filesystems
1.0 1.1.1.1 Ensure mounting of cramfs filesystems is disabled
1.0 1.1.1.2 Ensure mounting of freevxfs filesystems is disabled
1.0 1.1.1.3 Ensure mounting of jffs2 filesystems is disabled
1.0 1.1.1.4 Ensure mounting of hfs filesystems is disabled
1.0 1.1.1.5 Ensure mounting of hfsplus filesystems is disabled
1.0 1.1.1.6 Ensure mounting of udf filesystems is disabled
1.0 1.1.2 Ensure /tmp is configured
1.0 1.1.3 Ensure nodev option set on /tmp partition
1.0 1.1.4 Ensure nosuid option set on /tmp partition
1.0 1.1.5 Ensure noexec option set on /tmp partition
1.0 1.1.6 Ensure /dev/shm is configured
1.0 1.1.7 Ensure nodev option set on /dev/shm partition
1.0 1.1.8 Ensure nosuid option set on /dev/shm partition
1.0 1.1.9 Ensure noexec option set on /dev/shm partition
1.0 1.1.12 Ensure /var/tmp partition includes the nodev option
1.0 1.1.13 Ensure /var/tmp partition includes the nosuid option
1.0 1.1.14 Ensure /var/tmp partition includes the noexec option
1.0 1.1.18 Ensure /home partition includes the nodev option
1.1.19 Ensure nodev option set on removable media partitions
1.1.20 Ensure nosuid option set on removable media partitions
1.1.21 Ensure noexec option set on removable media partitions
1.0 1.1.22 Ensure sticky bit is set on all world-writable directories
1.0 1.1.23 Disable Automounting
1.0 1.1.24 Disable USB Storage
1.2 Configure Software Updates
1.2.1 Ensure package manager repositories are configured
1.2.2 Ensure GPG keys are configured
1.3 Filesystem Integrity Checking
1.0 1.3.1 Ensure AIDE is installed
1.0 1.3.2 Ensure filesystem integrity is regularly checked
1.4 Secure Boot Settings
1.0 1.4.1 Ensure permissions on bootloader config are not overridden
1.0 1.4.2 Ensure bootloader password is set
1.0 1.4.3 Ensure permissions on bootloader config are configured
1.0 1.4.4 Ensure authentication required for single user mode
1.5 Additional Process Hardening
1.5.1 Ensure XD/NX support is enabled
1.0 1.5.2 Ensure address space layout randomization (ASLR) is enabled
1.0 1.5.3 Ensure prelink is disabled
1.0 1.5.4 Ensure core dumps are restricted
1.6 Mandatory Access Control
1.6.1 Configure AppArmor
1.0 1.6.1.1 Ensure AppArmor is installed
1.0 1.6.1.2 Ensure AppArmor is enabled in the bootloader configuration
1.0 1.6.1.3 Ensure all AppArmor Profiles are in enforce or complain mode
1.7 Command Line Warning Banners
1.0 1.7.1 Ensure message of the day is configured properly
1.0 1.7.2 Ensure permissions on /etc/issue.net are configured
1.0 1.7.3 Ensure permissions on /etc/issue are configured
1.0 1.7.4 Ensure permissions on /etc/motd are configured
1.0 1.7.5 Ensure remote login warning banner is configured properly
1.0 1.7.6 Ensure local login warning banner is configured properly
1.8 GNOME Display Manager
1.0 1.8.2 Ensure GDM login banner is configured
1.0 1.8.3 Ensure disable-user-list is enabled
1.0 1.8.4 Ensure XDCMP is not enabled
1.9 Ensure updates, patches, and additional security software are installed
2 Services
2.1 Special Purpose Services
2.1.1 Time Synchronization
1.0 2.1.1.1 Ensure time synchronization is in use
2.1.1.2 Ensure systemd-timesyncd is configured
1.0 2.1.1.3 Ensure chrony is configured
1.0 2.1.1.4 Ensure ntp is configured
1.0 2.1.2 Ensure X Window System is not installed
1.0 2.1.3 Ensure Avahi Server is not installed
1.0 2.1.4 Ensure CUPS is not installed
1.0 2.1.5 Ensure DHCP Server is not installed
1.0 2.1.6 Ensure LDAP server is not installed
1.0 2.1.7 Ensure NFS is not installed
1.0 2.1.8 Ensure DNS Server is not installed
1.0 2.1.9 Ensure FTP Server is not installed
1.0 2.1.10 Ensure HTTP server is not installed
1.0 2.1.11 Ensure IMAP and POP3 server are not installed
1.0 2.1.12 Ensure Samba is not installed
1.0 2.1.13 Ensure HTTP Proxy Server is not installed
1.0 2.1.14 Ensure SNMP Server is not installed
1.0 2.1.15 Ensure mail transfer agent is configured for local-only mode
1.0 2.1.16 Ensure rsync service is not installed
1.0 2.1.17 Ensure NIS Server is not installed
2.2 Service Clients
1.0 2.2.1 Ensure NIS Client is not installed
1.0 2.2.2 Ensure rsh client is not installed
1.0 2.2.3 Ensure talk client is not installed
1.0 2.2.4 Ensure telnet client is not installed
1.0 2.2.5 Ensure LDAP client is not installed
1.0 2.2.6 Ensure RPC is not installed
2.3 Ensure nonessential services are removed or masked Manual
3 Network Configuration
3.1 Disable unused network protocols and devices
1.0 3.1.2 Ensure wireless interfaces are disabled
3.2 Network Parameters (Host Only)
1.0 3.2.1 Ensure packet redirect sending is disabled
1.0 3.2.2 Ensure IP forwarding is disabled Fail
3.3 Network Parameters (Host and Router)
1.0 3.3.1 Ensure source routed packets are not accepted
1.0 3.3.2 Ensure ICMP redirects are not accepted
1.0 3.3.3 Ensure secure ICMP redirects are not accepted
1.0 3.3.4 Ensure suspicious packets are logged
1.0 3.3.5 Ensure broadcast ICMP requests are ignored
1.0 3.3.6 Ensure bogus ICMP responses are ignored
1.0 3.3.7 Ensure Reverse Path Filtering is enabled
1.0 3.3.8 Ensure TCP SYN Cookies is enabled
1.0 3.3.9 Ensure IPv6 router advertisements are not accepted
3.4 Uncommon Network Protocols
3.5 Firewall Configuration
3.5.1 Configure UncomplicatedFirewall
1.0 3.5.1.1 Ensure ufw is installed
1.0 3.5.1.2 Ensure iptables-persistent is not installed with ufw
1.0 3.5.1.3 Ensure ufw service is enabled
1.0 3.5.1.4 Ensure ufw loopback traffic is configured
3.5.1.5 Ensure ufw outbound connections are configured
3.5.1.6 Ensure ufw firewall rules exist for all open ports
1.0 3.5.1.7 Ensure ufw default deny firewall policy
3.5.2 Configure nftables
1.0 3.5.2.1 Ensure nftables is installed
1.0 3.5.2.2 Ensure ufw is uninstalled or disabled with nftables
3.5.2.3 Ensure iptables are flushed with nftables
1.0 3.5.2.4 Ensure a nftables table exists
1.0 3.5.2.5 Ensure nftables base chains exist
1.0 3.5.2.6 Ensure nftables loopback traffic is configured
3.5.2.7 Ensure nftables outbound and established connections are configured
1.0 3.5.2.8 Ensure nftables default deny firewall policy
1.0 3.5.2.9 Ensure nftables service is enabled
1.0 3.5.2.10 Ensure nftables rules are permanent
3.5.3 Configure iptables
3.5.3.1 Configure iptables software
1.0 3.5.3.1.1 Ensure iptables packages are installed
1.0 3.5.3.1.2 Ensure nftables is not installed with iptables
1.0 3.5.3.1.3 Ensure ufw is uninstalled or disabled with iptables
3.5.3.2 Configure IPv4 iptables
1.0 3.5.3.2.1 Ensure iptables default deny firewall policy
1.0 3.5.3.2.2 Ensure iptables loopback traffic is configured
3.5.3.2.3 Ensure iptables outbound and established connections are configured
1.0 3.5.3.2.4 Ensure iptables firewall rules exist for all open ports
3.5.3.3 Configure IPv6 ip6tables
1.0 3.5.3.3.1 Ensure ip6tables default deny firewall policy
1.0 3.5.3.3.2 Ensure ip6tables loopback traffic is configured
3.5.3.3.3 Ensure ip6tables outbound and established connections are configured
1.0 3.5.3.3.4 Ensure ip6tables firewall rules exist for all open ports
4 Logging and Auditing
4.1 Configure System Accounting (auditd)
4.1.1 Ensure auditing is enabled
4.1.2 Configure Data Retention
4.2 Configure Logging
4.2.1 Configure rsyslog
1.0 4.2.1.1 Ensure rsyslog is installed
1.0 4.2.1.2 Ensure rsyslog Service is enabled
4.2.1.3 Ensure logging is configured
1.0 4.2.1.4 Ensure rsyslog default file permissions configured
1.0 4.2.1.5 Ensure rsyslog is configured to send logs to a remote log host
4.2.1.6 Ensure remote rsyslog messages are only accepted on designated log hosts.
4.2.2 Configure journald
1.0 4.2.2.1 Ensure journald is configured to send logs to rsyslog
1.0 4.2.2.2 Ensure journald is configured to compress large log files
1.0 4.2.2.3 Ensure journald is configured to write logfiles to persistent disk
1.0 4.2.3 Ensure permissions on all logfiles are configured
4.3 Ensure logrotate is configured
1.0 4.4 Ensure logrotate assigns appropriate permissions
5 Access, Authentication and Authorization
5.1 Configure time-based job schedulers
1.0 5.1.1 Ensure cron daemon is enabled and running
1.0 5.1.2 Ensure permissions on /etc/crontab are configured
1.0 5.1.3 Ensure permissions on /etc/cron.hourly are configured
1.0 5.1.4 Ensure permissions on /etc/cron.daily are configured
1.0 5.1.5 Ensure permissions on /etc/cron.weekly are configured
1.0 5.1.6 Ensure permissions on /etc/cron.monthly are configured
1.0 5.1.7 Ensure permissions on /etc/cron.d are configured
1.0 5.1.8 Ensure cron is restricted to authorized users
1.0 5.1.9 Ensure at is restricted to authorized users
5.2 Configure sudo
1.0 5.2.1 Ensure sudo is installed
1.0 5.2.2 Ensure sudo commands use pty
1.0 5.2.3 Ensure sudo log file exists
5.3 Configure SSH Server
1.0 5.3.1 Ensure permissions on /etc/ssh/sshd_config are configured
1.0 5.3.2 Ensure permissions on SSH private host key files are configured
1.0 5.3.3 Ensure permissions on SSH public host key files are configured
1.0 5.3.4 Ensure SSH access is limited
1.0 5.3.5 Ensure SSH LogLevel is appropriate
1.0 5.3.7 Ensure SSH MaxAuthTries is set to 4 or less
1.0 5.3.8 Ensure SSH IgnoreRhosts is enabled
1.0 5.3.9 Ensure SSH HostbasedAuthentication is disabled
1.0 5.3.10 Ensure SSH root login is disabled
1.0 5.3.11 Ensure SSH PermitEmptyPasswords is disabled
1.0 5.3.12 Ensure SSH PermitUserEnvironment is disabled
1.0 5.3.13 Ensure only strong Ciphers are used
1.0 5.3.14 Ensure only strong MAC algorithms are used
1.0 5.3.15 Ensure only strong Key Exchange algorithms are used
1.0 5.3.16 Ensure SSH Idle Timeout Interval is configured
1.0 5.3.17 Ensure SSH LoginGraceTime is set to one minute or less
1.0 5.3.18 Ensure SSH warning banner is configured
1.0 5.3.19 Ensure SSH PAM is enabled
1.0 5.3.21 Ensure SSH MaxStartups is configured
1.0 5.3.22 Ensure SSH MaxSessions is limited
5.4 Configure PAM
1.0 5.4.1 Ensure password creation requirements are configured
1.0 5.4.2 Ensure lockout for failed password attempts is configured
1.0 5.4.3 Ensure password reuse is limited
1.0 5.4.4 Ensure password hashing algorithm is SHA-512
5.5 User Accounts and Environment
5.5.1 Set Shadow Password Suite Parameters
1.0 5.5.1.1 Ensure minimum days between password changes is configured
1.0 5.5.1.2 Ensure password expiration is 365 days or less
1.0 5.5.1.3 Ensure password expiration warning days is 7 or more
1.0 5.5.1.4 Ensure inactive password lock is 30 days or less
1.0 5.5.1.5 Ensure all users last password change date is in the past
1.0 5.5.2 Ensure system accounts are secured
1.0 5.5.3 Ensure default group for the root account is GID 0
1.0 5.5.4 Ensure default user umask is 027 or more restrictive
1.0 5.5.5 Ensure default user shell timeout is 900 seconds or less
5.6 Ensure root login is restricted to system console
1.0 5.7 Ensure access to the su command is restricted
6 System Maintenance
6.1 System File Permissions
1.0 6.1.2 Ensure permissions on /etc/passwd are configured
1.0 6.1.3 Ensure permissions on /etc/passwd- are configured
1.0 6.1.4 Ensure permissions on /etc/group are configured
1.0 6.1.5 Ensure permissions on /etc/group- are configured
1.0 6.1.6 Ensure permissions on /etc/shadow are configured
1.0 6.1.7 Ensure permissions on /etc/shadow- are configured
1.0 6.1.8 Ensure permissions on /etc/gshadow are configured
1.0 6.1.9 Ensure permissions on /etc/gshadow- are configured
1.0 6.1.10 Ensure no world writable files exist
1.0 6.1.11 Ensure no unowned files or directories exist
1.0 6.1.12 Ensure no ungrouped files or directories exist
6.1.13 Audit SUID executables Manual
6.1.14 Audit SGID executables Manual
6.2 User and Group Settings
1.0 6.2.1 Ensure accounts in /etc/passwd use shadowed passwords
1.0 6.2.2 Ensure password fields are not empty
1.0 6.2.3 Ensure all groups in /etc/passwd exist in /etc/group
1.0 6.2.4 Ensure all users’ home directories exist
1.0 6.2.5 Ensure users own their home directories
1.0 6.2.6 Ensure users’ home directories permissions are 750 or more restrictive
1.0 6.2.7 Ensure users’ dot files are not group or world writable
1.0 6.2.8 Ensure no users have .netrc files
1.0 6.2.9 Ensure no users have .forward files
1.0 6.2.10 Ensure no users have .rhosts files
1.0 6.2.11 Ensure root is the only UID 0 account
1.0 6.2.12 Ensure root PATH Integrity
1.0 6.2.13 Ensure no duplicate UIDs exist
1.0 6.2.14 Ensure no duplicate GIDs exist
1.0 6.2.15 Ensure no duplicate user names exist
1.0 6.2.16 Ensure no duplicate group names exist
1.0 6.2.17 Ensure shadow group is empty

Hello?
Do you know if any other file than the dtb and the /boot/extlinux/extlinux.conf file could affect the SPI interface?
Any clue on what next debugging steps I could try?

Thanks!

Could you check the below command after apply the dtb file.

sudo cat /sys/kernel/debug/tegra_gpio

This is the output that I get:

Port:Pin:ENB DBC IN OUT_CTRL OUT_VAL INT_CLR
A:0 0x0 0x0 0x0 0x1 0x0 0x0
A:1 0x0 0x0 0x0 0x1 0x0 0x0
A:2 0x0 0x0 0x0 0x1 0x0 0x0
A:3 0x0 0x0 0x0 0x1 0x0 0x0
A:4 0x0 0x0 0x0 0x1 0x0 0x0
A:5 0x0 0x0 0x0 0x1 0x0 0x0
A:6 0x0 0x0 0x0 0x1 0x0 0x0
A:7 0x0 0x0 0x0 0x1 0x0 0x0
B:0 0x3 0x0 0x0 0x0 0x1 0x0
B:1 0x0 0x0 0x0 0x1 0x0 0x0
C:0 0x0 0x0 0x0 0x1 0x0 0x0
C:1 0x0 0x0 0x0 0x1 0x0 0x0
C:2 0x0 0x0 0x0 0x1 0x0 0x0
C:3 0x0 0x0 0x0 0x1 0x0 0x0
C:4 0x0 0x0 0x0 0x1 0x0 0x0
C:5 0x0 0x0 0x0 0x1 0x0 0x0
C:6 0x0 0x0 0x0 0x1 0x0 0x0
C:7 0x0 0x0 0x0 0x1 0x0 0x0
D:0 0x0 0x0 0x0 0x1 0x0 0x0
D:1 0x0 0x0 0x0 0x1 0x0 0x0
D:2 0x0 0x0 0x0 0x1 0x0 0x0
D:3 0x0 0x0 0x0 0x1 0x0 0x0
E:0 0x0 0x0 0x0 0x1 0x0 0x0
E:1 0x0 0x0 0x0 0x1 0x0 0x0
E:2 0x0 0x0 0x0 0x1 0x0 0x0
E:3 0x0 0x0 0x0 0x1 0x0 0x0
E:4 0x0 0x0 0x0 0x1 0x0 0x0
E:5 0x0 0x0 0x0 0x1 0x0 0x0
E:6 0x0 0x0 0x0 0x1 0x0 0x0
E:7 0x0 0x0 0x0 0x1 0x0 0x0
F:0 0x0 0x0 0x0 0x1 0x0 0x0
F:1 0x0 0x0 0x0 0x1 0x0 0x0
F:2 0x0 0x0 0x0 0x1 0x0 0x0
F:3 0x0 0x0 0x0 0x1 0x0 0x0
F:4 0x0 0x0 0x0 0x1 0x0 0x0
F:5 0x0 0x0 0x0 0x1 0x0 0x0
G:0 0x6d 0x5 0x1 0x1 0x0 0x0
G:1 0x0 0x0 0x0 0x1 0x0 0x0
G:2 0x3 0x0 0x0 0x0 0x1 0x0
G:3 0x3 0x0 0x0 0x0 0x1 0x0
G:4 0x45 0x0 0x1 0x1 0x0 0x0
G:5 0x0 0x0 0x0 0x1 0x0 0x0
G:6 0x0 0x0 0x0 0x1 0x0 0x0
G:7 0x4d 0x0 0x0 0x0 0x0 0x0
H:0 0x0 0x0 0x0 0x1 0x0 0x0
H:1 0x0 0x0 0x0 0x1 0x0 0x0
H:2 0x0 0x0 0x0 0x1 0x0 0x0
H:3 0x1 0x0 0x0 0x1 0x0 0x0
H:4 0x0 0x0 0x0 0x1 0x0 0x0
H:5 0x1 0x0 0x1 0x1 0x0 0x0
H:6 0x0 0x0 0x0 0x1 0x0 0x0
H:7 0x0 0x0 0x0 0x1 0x0 0x0
I:0 0x0 0x0 0x0 0x1 0x0 0x0
I:1 0x0 0x0 0x0 0x1 0x0 0x0
I:2 0x0 0x0 0x0 0x1 0x0 0x0
I:3 0x0 0x0 0x0 0x1 0x0 0x0
I:4 0x0 0x0 0x0 0x1 0x0 0x0
J:0 0x0 0x0 0x0 0x1 0x0 0x0
J:1 0x0 0x0 0x0 0x1 0x0 0x0
J:2 0x0 0x0 0x0 0x1 0x0 0x0
J:3 0x0 0x0 0x0 0x1 0x0 0x0
J:4 0x0 0x0 0x0 0x1 0x0 0x0
J:5 0x0 0x0 0x0 0x1 0x0 0x0
K:0 0x0 0x0 0x0 0x1 0x0 0x0
K:1 0x0 0x0 0x0 0x1 0x0 0x0
K:2 0x0 0x0 0x0 0x1 0x0 0x0
K:3 0x0 0x0 0x0 0x1 0x0 0x0
K:4 0x0 0x0 0x0 0x1 0x0 0x0
K:5 0x0 0x0 0x0 0x1 0x0 0x0
K:6 0x0 0x0 0x0 0x1 0x0 0x0
K:7 0x0 0x0 0x0 0x1 0x0 0x0
L:0 0x0 0x0 0x0 0x1 0x0 0x0
L:1 0x0 0x0 0x0 0x1 0x0 0x0
L:2 0x1 0x0 0x1 0x1 0x0 0x0
L:3 0x0 0x0 0x0 0x1 0x0 0x0
M:0 0x0 0x0 0x0 0x1 0x0 0x0
M:1 0x4d 0x0 0x1 0x0 0x0 0x0
M:2 0x0 0x0 0x0 0x1 0x0 0x0
M:3 0x0 0x0 0x0 0x1 0x0 0x0
M:4 0x0 0x0 0x0 0x1 0x0 0x0
M:5 0x0 0x0 0x0 0x1 0x0 0x0
M:6 0x0 0x0 0x0 0x1 0x0 0x0
M:7 0x0 0x0 0x0 0x1 0x0 0x0
N:0 0x3 0x0 0x0 0x0 0x0 0x0
N:1 0x1 0x0 0x0 0x1 0x0 0x0
N:2 0x0 0x0 0x0 0x1 0x0 0x0
O:0 0x0 0x0 0x0 0x1 0x0 0x0
O:1 0x0 0x0 0x0 0x1 0x0 0x0
O:2 0x0 0x0 0x0 0x1 0x0 0x0
O:3 0x0 0x0 0x0 0x1 0x0 0x0
O:4 0x0 0x0 0x0 0x1 0x0 0x0
O:5 0x0 0x0 0x0 0x1 0x0 0x0
P:0 0x0 0x0 0x0 0x1 0x0 0x0
P:1 0x0 0x0 0x0 0x1 0x0 0x0
P:2 0x0 0x0 0x0 0x1 0x0 0x0
P:3 0x0 0x0 0x0 0x1 0x0 0x0
P:4 0x3 0x0 0x0 0x0 0x0 0x0
P:5 0x3 0x0 0x0 0x0 0x0 0x0
P:6 0x0 0x0 0x0 0x1 0x0 0x0
P:7 0x0 0x0 0x0 0x1 0x0 0x0
Q:0 0x0 0x0 0x0 0x1 0x0 0x0
Q:1 0x1 0x0 0x1 0x1 0x0 0x0
Q:2 0x0 0x0 0x0 0x1 0x0 0x0
Q:3 0x1 0x0 0x1 0x1 0x0 0x0
Q:4 0x0 0x0 0x0 0x1 0x0 0x0
Q:5 0x1 0x0 0x0 0x1 0x0 0x0
Q:6 0x1 0x0 0x0 0x1 0x0 0x0
Q:7 0x0 0x0 0x0 0x1 0x0 0x0
R:0 0x1 0x0 0x0 0x1 0x0 0x0
R:1 0x3 0x0 0x0 0x0 0x1 0x0
R:2 0x0 0x0 0x0 0x1 0x0 0x0
R:3 0x0 0x0 0x0 0x1 0x0 0x0
R:4 0x1 0x0 0x0 0x1 0x0 0x0
R:5 0x1 0x0 0x1 0x1 0x0 0x0
S:0 0x0 0x0 0x0 0x1 0x0 0x0
S:1 0x0 0x0 0x0 0x1 0x0 0x0
S:2 0x0 0x0 0x0 0x1 0x0 0x0
S:3 0x0 0x0 0x0 0x1 0x0 0x0
S:4 0x1 0x0 0x0 0x1 0x0 0x0
S:5 0x0 0x0 0x0 0x1 0x0 0x0
S:6 0x0 0x0 0x0 0x1 0x0 0x0
S:7 0x1 0x0 0x0 0x1 0x0 0x0
T:0 0x0 0x0 0x0 0x1 0x0 0x0
T:1 0x0 0x0 0x0 0x1 0x0 0x0
T:2 0x0 0x0 0x0 0x1 0x0 0x0
T:3 0x0 0x0 0x0 0x1 0x0 0x0
T:4 0x0 0x0 0x0 0x1 0x0 0x0
T:5 0x1 0x0 0x0 0x1 0x0 0x0
T:6 0x1 0x0 0x0 0x1 0x0 0x0
T:7 0x1 0x0 0x1 0x1 0x0 0x0
U:0 0x1 0x0 0x0 0x1 0x0 0x0
V:0 0x0 0x0 0x0 0x1 0x0 0x0
V:1 0x0 0x0 0x0 0x1 0x0 0x0
V:2 0x0 0x0 0x0 0x1 0x0 0x0
V:3 0x0 0x0 0x0 0x1 0x0 0x0
V:4 0x0 0x0 0x0 0x1 0x0 0x0
V:5 0x0 0x0 0x0 0x1 0x0 0x0
V:6 0x0 0x0 0x0 0x1 0x0 0x0
V:7 0x0 0x0 0x0 0x1 0x0 0x0
W:0 0x0 0x0 0x0 0x1 0x0 0x0
W:1 0x0 0x0 0x0 0x1 0x0 0x0
X:2 0x0 0x0 0x0 0x1 0x0 0x0
X:3 0x0 0x0 0x0 0x1 0x0 0x0
X:4 0x0 0x0 0x0 0x1 0x0 0x0
X:5 0x0 0x0 0x0 0x1 0x0 0x0
X:6 0x0 0x0 0x0 0x1 0x0 0x0
X:7 0x0 0x0 0x0 0x1 0x0 0x0
Y:0 0x1 0x0 0x0 0x1 0x0 0x0
Y:1 0x1 0x0 0x0 0x1 0x0 0x0
Y:2 0x1 0x0 0x0 0x1 0x0 0x0
Y:3 0x1 0x0 0x0 0x1 0x0 0x0
Y:4 0x1 0x0 0x0 0x1 0x0 0x0
Y:5 0x1 0x0 0x0 0x1 0x0 0x0
Y:6 0x0 0x0 0x0 0x1 0x0 0x0
Y:7 0x1 0x0 0x0 0x1 0x0 0x0
Z:0 0x0 0x0 0x0 0x1 0x0 0x0
Z:1 0x4d 0x0 0x1 0x1 0x0 0x0
Z:2 0x0 0x0 0x0 0x1 0x0 0x0
Z:3 0x1 0x0 0x0 0x1 0x0 0x0
Z:4 0x1 0x0 0x0 0x1 0x0 0x0
Z:5 0x1 0x0 0x0 0x1 0x0 0x0
Z:6 0x1 0x0 0x0 0x1 0x0 0x0
Z:7 0x1 0x0 0x0 0x1 0x0 0x0
FF:0 0x0 0x0 0x0 0x1 0x0 0x0
FF:1 0x0 0x0 0x0 0x1 0x0 0x0
GG:0 0x0 0x0 0x0 0x1 0x0 0x0
GG:1 0x0 0x0 0x0 0x1 0x0 0x0

Sorry I thought it’s Nano need to confirm the GPIO configure.
For NX doesn’t need to care about this.
Maybe you can check the PINMUX REG by devmem2.

Hi,

This is the output of sudo cat /sys/kernel/debug/tegra_pinctrl_reg:

Bank: 1 Reg: 0x0c302000 Val: 0x00000056 → touch_clk_pcc4
Bank: 1 Reg: 0x0c302008 Val: 0x00000450 → uart3_rx_pcc6
Bank: 1 Reg: 0x0c302010 Val: 0x00000400 → uart3_tx_pcc5
Bank: 1 Reg: 0x0c302018 Val: 0x00000560 → gen8_i2c_sda_pdd2
Bank: 1 Reg: 0x0c302020 Val: 0x00000560 → gen8_i2c_scl_pdd1
Bank: 1 Reg: 0x0c302028 Val: 0x00000002 → spi2_mosi_pcc2
Bank: 1 Reg: 0x0c302030 Val: 0x00000460 → gen2_i2c_scl_pcc7
Bank: 1 Reg: 0x0c302038 Val: 0x00000002 → spi2_cs0_pcc3
Bank: 1 Reg: 0x0c302040 Val: 0x00000460 → gen2_i2c_sda_pdd0
Bank: 1 Reg: 0x0c302048 Val: 0x00000002 → spi2_sck_pcc0
Bank: 1 Reg: 0x0c302050 Val: 0x00000002 → spi2_miso_pcc1
Bank: 1 Reg: 0x0c303000 Val: 0x0000c415 → can1_dout_paa0
Bank: 1 Reg: 0x0c303008 Val: 0x0000c415 → can1_din_paa1
Bank: 1 Reg: 0x0c303010 Val: 0x0000c400 → can0_dout_paa2
Bank: 1 Reg: 0x0c303018 Val: 0x0000c450 → can0_din_paa3
Bank: 1 Reg: 0x0c303020 Val: 0x0000c414 → can0_stb_paa4
Bank: 1 Reg: 0x0c303028 Val: 0x0000c000 → can0_en_paa5
Bank: 1 Reg: 0x0c303030 Val: 0x0000c414 → can0_wake_paa6
Bank: 1 Reg: 0x0c303038 Val: 0x0000c414 → can0_err_paa7
Bank: 1 Reg: 0x0c303040 Val: 0x0000c414 → can1_stb_pbb0
Bank: 1 Reg: 0x0c303048 Val: 0x0000c414 → can1_en_pbb1
Bank: 1 Reg: 0x0c303050 Val: 0x0000c414 → can1_wake_pbb2
Bank: 1 Reg: 0x0c303058 Val: 0x0000c414 → can1_err_pbb3
Bank: 0 Reg: 0x02431000 Val: 0x00000414 → soc_gpio33_pt0
Bank: 0 Reg: 0x02431008 Val: 0x00000058 → soc_gpio32_ps7
Bank: 0 Reg: 0x02431010 Val: 0x00000414 → soc_gpio31_ps6
Bank: 0 Reg: 0x02431018 Val: 0x00000414 → soc_gpio30_ps5
Bank: 0 Reg: 0x02431020 Val: 0x00000059 → aud_mclk_ps4
Bank: 0 Reg: 0x02431028 Val: 0x00000415 → dap1_fs_ps3
Bank: 0 Reg: 0x02431030 Val: 0x00000415 → dap1_din_ps2
Bank: 0 Reg: 0x02431038 Val: 0x00000415 → dap1_dout_ps1
Bank: 0 Reg: 0x02431040 Val: 0x00000415 → dap1_sclk_ps0
Bank: 0 Reg: 0x02431048 Val: 0x00000440 → dap3_fs_pt4
Bank: 0 Reg: 0x02431050 Val: 0x00000450 → dap3_din_pt3
Bank: 0 Reg: 0x02431058 Val: 0x00000400 → dap3_dout_pt2
Bank: 0 Reg: 0x02431060 Val: 0x00000440 → dap3_sclk_pt1
Bank: 0 Reg: 0x02431068 Val: 0x00000057 → dap5_fs_pu0
Bank: 0 Reg: 0x02431070 Val: 0x00000057 → dap5_din_pt7
Bank: 0 Reg: 0x02431078 Val: 0x00000056 → dap5_dout_pt6
Bank: 0 Reg: 0x02431080 Val: 0x00000056 → dap5_sclk_pt5
Bank: 0 Reg: 0x02432000 Val: 0x0000c416 → dap6_fs_pa3
Bank: 0 Reg: 0x02432008 Val: 0x0000c416 → dap6_din_pa2
Bank: 0 Reg: 0x02432010 Val: 0x0000c416 → dap6_dout_pa1
Bank: 0 Reg: 0x02432018 Val: 0x0000c416 → dap6_sclk_pa0
Bank: 0 Reg: 0x02432020 Val: 0x0000c416 → dap4_fs_pa7
Bank: 0 Reg: 0x02432028 Val: 0x0000c416 → dap4_din_pa6
Bank: 0 Reg: 0x02432030 Val: 0x0000c416 → dap4_dout_pa5
Bank: 0 Reg: 0x02432038 Val: 0x0000c416 → dap4_sclk_pa4
Bank: 0 Reg: 0x02430000 Val: 0x00000400 → extperiph2_clk_pp1
Bank: 0 Reg: 0x02430008 Val: 0x00000400 → extperiph1_clk_pp0
Bank: 0 Reg: 0x02430010 Val: 0x00000460 → cam_i2c_sda_pp3
Bank: 0 Reg: 0x02430018 Val: 0x00000460 → cam_i2c_scl_pp2
Bank: 0 Reg: 0x02430020 Val: 0x00000426 → soc_gpio40_pq4
Bank: 0 Reg: 0x02430028 Val: 0x0000005a → soc_gpio41_pq5
Bank: 0 Reg: 0x02430030 Val: 0x0000005a → soc_gpio42_pq6
Bank: 0 Reg: 0x02430038 Val: 0x00000426 → soc_gpio43_pq7
Bank: 0 Reg: 0x02430040 Val: 0x00000056 → soc_gpio44_pr0
Bank: 0 Reg: 0x02430048 Val: 0x00000021 → soc_gpio45_pr1
Bank: 0 Reg: 0x02430050 Val: 0x00000414 → soc_gpio20_pq0
Bank: 0 Reg: 0x02430058 Val: 0x00000054 → soc_gpio21_pq1
Bank: 0 Reg: 0x02430060 Val: 0x00000459 → soc_gpio22_pq2
Bank: 0 Reg: 0x02430068 Val: 0x00000058 → soc_gpio23_pq3
Bank: 0 Reg: 0x02430070 Val: 0x00000000 → soc_gpio04_pp4
Bank: 0 Reg: 0x02430078 Val: 0x00000000 → soc_gpio05_pp5
Bank: 0 Reg: 0x02430080 Val: 0x00000414 → soc_gpio06_pp6
Bank: 0 Reg: 0x02430088 Val: 0x0000045a → soc_gpio07_pp7
Bank: 0 Reg: 0x02430090 Val: 0x00000055 → uart1_cts_pr5
Bank: 0 Reg: 0x02430098 Val: 0x00000055 → uart1_rts_pr4
Bank: 0 Reg: 0x024300a0 Val: 0x00000454 → uart1_rx_pr3
Bank: 0 Reg: 0x024300a8 Val: 0x00000400 → uart1_tx_pr2
Bank: 0 Reg: 0x02434000 Val: 0x00000415 → dap2_din_pi1
Bank: 0 Reg: 0x02434008 Val: 0x00000415 → dap2_dout_pi0
Bank: 0 Reg: 0x02434010 Val: 0x00000415 → dap2_fs_pi2
Bank: 0 Reg: 0x02434018 Val: 0x00000415 → dap2_sclk_ph7
Bank: 0 Reg: 0x02434020 Val: 0x00000415 → uart4_cts_ph6
Bank: 0 Reg: 0x02434028 Val: 0x00000051 → uart4_rts_ph5
Bank: 0 Reg: 0x02434030 Val: 0x00000415 → uart4_rx_ph4
Bank: 0 Reg: 0x02434038 Val: 0x00000051 → uart4_tx_ph3
Bank: 0 Reg: 0x02434040 Val: 0x00000004 → soc_gpio03_pg3
Bank: 0 Reg: 0x02434048 Val: 0x00000000 → soc_gpio02_pg2
Bank: 0 Reg: 0x02434050 Val: 0x00000414 → soc_gpio01_pg1
Bank: 0 Reg: 0x02434058 Val: 0x00000058 → soc_gpio00_pg0
Bank: 0 Reg: 0x02434060 Val: 0x00000540 → gen1_i2c_scl_pi3
Bank: 0 Reg: 0x02434068 Val: 0x00000540 → gen1_i2c_sda_pi4
Bank: 0 Reg: 0x02434070 Val: 0x00000050 → soc_gpio08_pg4
Bank: 0 Reg: 0x02434078 Val: 0x00000414 → soc_gpio09_pg5
Bank: 0 Reg: 0x02434080 Val: 0x00000400 → soc_gpio10_pg6
Bank: 0 Reg: 0x02434088 Val: 0x00000058 → soc_gpio11_pg7
Bank: 0 Reg: 0x02434090 Val: 0x00000414 → soc_gpio12_ph0
Bank: 0 Reg: 0x02434098 Val: 0x00000401 → soc_gpio13_ph1
Bank: 0 Reg: 0x024340a0 Val: 0x00000414 → soc_gpio14_ph2
Bank: 0 Reg: 0x02435008 Val: 0x00022414 → directdc1_out7_pw1
Bank: 0 Reg: 0x02435010 Val: 0x00022414 → directdc1_out6_pw0
Bank: 0 Reg: 0x02435018 Val: 0x00022414 → directdc1_out5_pv7
Bank: 0 Reg: 0x02435020 Val: 0x00022414 → directdc1_out4_pv6
Bank: 0 Reg: 0x02435028 Val: 0x00022414 → directdc1_out3_pv5
Bank: 0 Reg: 0x02435030 Val: 0x00022414 → directdc1_out2_pv4
Bank: 0 Reg: 0x02435038 Val: 0x00022414 → directdc1_out1_pv3
Bank: 0 Reg: 0x02435040 Val: 0x00022414 → directdc1_out0_pv2
Bank: 0 Reg: 0x02435048 Val: 0x00022454 → directdc1_in_pv1
Bank: 0 Reg: 0x02435050 Val: 0x00022414 → directdc1_clk_pv0
Bank: 0 Reg: 0x02435058 Val: 0x00002000 → directdc_comp
Bank: 0 Reg: 0x02440000 Val: 0x00000414 → soc_gpio50_pm5
Bank: 0 Reg: 0x02440008 Val: 0x00000414 → soc_gpio51_pm6
Bank: 0 Reg: 0x02440010 Val: 0x00000414 → soc_gpio52_pm7
Bank: 0 Reg: 0x02440018 Val: 0x00000004 → soc_gpio53_pn0
Bank: 0 Reg: 0x02440020 Val: 0x00000054 → soc_gpio54_pn1
Bank: 0 Reg: 0x02440028 Val: 0x00000414 → soc_gpio55_pn2
Bank: 0 Reg: 0x02440030 Val: 0x00000450 → dp_aux_ch0_hpd_pm0
Bank: 0 Reg: 0x02440038 Val: 0x00000150 → dp_aux_ch1_hpd_pm1
Bank: 0 Reg: 0x02440040 Val: 0x00000416 → dp_aux_ch2_hpd_pm2
Bank: 0 Reg: 0x02440048 Val: 0x00000416 → dp_aux_ch3_hpd_pm3
Bank: 0 Reg: 0x02440050 Val: 0x00000460 → hdmi_cec_pm4
Bank: 0 Reg: 0x02445000 Val: 0x00022400 → eqos_td3_pe4
Bank: 0 Reg: 0x02445008 Val: 0x00022400 → eqos_td2_pe3
Bank: 0 Reg: 0x02445010 Val: 0x00022400 → eqos_td1_pe2
Bank: 0 Reg: 0x02445018 Val: 0x00022400 → eqos_td0_pe1
Bank: 0 Reg: 0x02445020 Val: 0x00022440 → eqos_rd3_pf1
Bank: 0 Reg: 0x02445028 Val: 0x00022440 → eqos_rd2_pf0
Bank: 0 Reg: 0x02445030 Val: 0x00022440 → eqos_rd1_pe7
Bank: 0 Reg: 0x02445038 Val: 0x00022440 → eqos_sma_mdio_pf4
Bank: 0 Reg: 0x02445040 Val: 0x00022440 → eqos_rd0_pe6
Bank: 0 Reg: 0x02445048 Val: 0x00022400 → eqos_sma_mdc_pf5
Bank: 0 Reg: 0x02445050 Val: 0x00002000 → eqos_comp
Bank: 0 Reg: 0x02445058 Val: 0x00022400 → eqos_txc_pe0
Bank: 0 Reg: 0x02445060 Val: 0x00022440 → eqos_rxc_pf3
Bank: 0 Reg: 0x02445068 Val: 0x00022400 → eqos_tx_ctl_pe5
Bank: 0 Reg: 0x02445070 Val: 0x00022440 → eqos_rx_ctl_pf2
Bank: 0 Reg: 0x02437000 Val: 0x00000415 → pex_l2_clkreq_n_pk4
Bank: 0 Reg: 0x02437008 Val: 0x00000178 → pex_wake_n_pl2
Bank: 0 Reg: 0x02437010 Val: 0x00000415 → pex_l1_clkreq_n_pk2
Bank: 0 Reg: 0x02437018 Val: 0x00000415 → pex_l1_rst_n_pk3
Bank: 0 Reg: 0x02437020 Val: 0x00000415 → pex_l0_clkreq_n_pk0
Bank: 0 Reg: 0x02437028 Val: 0x00000415 → pex_l0_rst_n_pk1
Bank: 0 Reg: 0x02437030 Val: 0x00000415 → pex_l2_rst_n_pk5
Bank: 0 Reg: 0x02437038 Val: 0x00000415 → pex_l3_clkreq_n_pk6
Bank: 0 Reg: 0x02437040 Val: 0x00000415 → pex_l3_rst_n_pk7
Bank: 0 Reg: 0x02437048 Val: 0x00000560 → pex_l4_clkreq_n_pl0
Bank: 0 Reg: 0x02437050 Val: 0x00000520 → pex_l4_rst_n_pl1
Bank: 0 Reg: 0x02437058 Val: 0x00000415 → sata_dev_slp_pl3
Bank: 0 Reg: 0x02444000 Val: 0x00000560 → pex_l5_clkreq_n_pgg0
Bank: 0 Reg: 0x02444008 Val: 0x00000520 → pex_l5_rst_n_pgg1
Bank: 0 Reg: 0x02446000 Val: 0x00000414 → cpu_pwr_req_1_pb1
Bank: 0 Reg: 0x02446008 Val: 0x00000000 → cpu_pwr_req_0_pb0
Bank: 0 Reg: 0x0243b000 Val: 0x00023440 → qspi0_io3_pc5
Bank: 0 Reg: 0x0243b008 Val: 0x00023440 → qspi0_io2_pc4
Bank: 0 Reg: 0x0243b010 Val: 0x00023440 → qspi0_io1_pc3
Bank: 0 Reg: 0x0243b018 Val: 0x00023440 → qspi0_io0_pc2
Bank: 0 Reg: 0x0243b020 Val: 0x00023460 → qspi0_sck_pc0
Bank: 0 Reg: 0x0243b028 Val: 0x00023400 → qspi0_cs_n_pc1
Bank: 0 Reg: 0x0243b030 Val: 0x00023415 → qspi1_io3_pd3
Bank: 0 Reg: 0x0243b038 Val: 0x00023415 → qspi1_io2_pd2
Bank: 0 Reg: 0x0243b040 Val: 0x00023415 → qspi1_io1_pd1
Bank: 0 Reg: 0x0243b048 Val: 0x00023415 → qspi1_io0_pd0
Bank: 0 Reg: 0x0243b050 Val: 0x00023435 → qspi1_sck_pc6
Bank: 0 Reg: 0x0243b058 Val: 0x00023415 → qspi1_cs_n_pc7
Bank: 0 Reg: 0x0243b060 Val: 0x00002000 → qspi_comp
Bank: 0 Reg: 0x02438000 Val: 0x0000a460 → sdmmc1_clk_pj0
Bank: 0 Reg: 0x02438008 Val: 0x0000a448 → sdmmc1_cmd_pj1
Bank: 0 Reg: 0x02438010 Val: 0x00000000 → sdmmc1_comp
Bank: 0 Reg: 0x02438018 Val: 0x0000a448 → sdmmc1_dat3_pj5
Bank: 0 Reg: 0x02438020 Val: 0x0000a448 → sdmmc1_dat2_pj4
Bank: 0 Reg: 0x02438028 Val: 0x0000a448 → sdmmc1_dat1_pj3
Bank: 0 Reg: 0x02438030 Val: 0x0000a448 → sdmmc1_dat0_pj2
Bank: 0 Reg: 0x0243a000 Val: 0x0000a448 → sdmmc3_dat3_po5
Bank: 0 Reg: 0x0243a008 Val: 0x0000a448 → sdmmc3_dat2_po4
Bank: 0 Reg: 0x0243a010 Val: 0x0000a448 → sdmmc3_dat1_po3
Bank: 0 Reg: 0x0243a018 Val: 0x0000a448 → sdmmc3_dat0_po2
Bank: 0 Reg: 0x0243a020 Val: 0x00000000 → sdmmc3_comp
Bank: 0 Reg: 0x0243a028 Val: 0x0000a448 → sdmmc3_cmd_po1
Bank: 0 Reg: 0x0243a030 Val: 0x0000a460 → sdmmc3_clk_po0
Bank: 0 Reg: 0x02436008 Val: 0x00002060 → sdmmc4_clk
Bank: 0 Reg: 0x02436010 Val: 0x00002040 → sdmmc4_cmd
Bank: 0 Reg: 0x02436018 Val: 0x00000040 → sdmmc4_dqs
Bank: 0 Reg: 0x02436020 Val: 0x00002048 → sdmmc4_dat7
Bank: 0 Reg: 0x02436028 Val: 0x00002048 → sdmmc4_dat6
Bank: 0 Reg: 0x02436030 Val: 0x00002048 → sdmmc4_dat5
Bank: 0 Reg: 0x02436038 Val: 0x00002048 → sdmmc4_dat4
Bank: 0 Reg: 0x02436040 Val: 0x00002048 → sdmmc4_dat3
Bank: 0 Reg: 0x02436048 Val: 0x00002048 → sdmmc4_dat2
Bank: 0 Reg: 0x02436050 Val: 0x00002048 → sdmmc4_dat1
Bank: 0 Reg: 0x02436058 Val: 0x00002048 → sdmmc4_dat0
Bank: 1 Reg: 0x0c301000 Val: 0x00000000 → shutdown_n
Bank: 1 Reg: 0x0c301008 Val: 0x00000040 → pmu_int_n
Bank: 1 Reg: 0x0c301010 Val: 0x00000051 → safe_state_pee0
Bank: 1 Reg: 0x0c301018 Val: 0x00000458 → vcomp_alert_pee1
Bank: 1 Reg: 0x0c301020 Val: 0x00000000 → soc_pwr_req
Bank: 1 Reg: 0x0c301028 Val: 0x00000458 → batt_oc_pee3
Bank: 1 Reg: 0x0c301030 Val: 0x00001000 → clk_32k_in
Bank: 1 Reg: 0x0c301038 Val: 0x00000058 → power_on_pee4
Bank: 1 Reg: 0x0c301040 Val: 0x00000440 → pwr_i2c_scl_pee5
Bank: 1 Reg: 0x0c301048 Val: 0x00000440 → pwr_i2c_sda_pee6
Bank: 1 Reg: 0x0c301060 Val: 0x00000415 → ao_retention_n_pee2
Bank: 0 Reg: 0x0243d000 Val: 0x00000000 → gpu_pwr_req_px0
Bank: 0 Reg: 0x0243d008 Val: 0x00000055 → spi3_miso_py1
Bank: 0 Reg: 0x0243d010 Val: 0x00000448 → spi1_cs0_pz6
Bank: 0 Reg: 0x0243d018 Val: 0x00000055 → spi3_cs0_py3
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 → spi1_miso_pz4
Bank: 0 Reg: 0x0243d028 Val: 0x00000055 → spi3_cs1_py4
Bank: 0 Reg: 0x0243d030 Val: 0x00000415 → gp_pwm3_px3
Bank: 0 Reg: 0x0243d038 Val: 0x00000400 → gp_pwm2_px2
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 → spi1_sck_pz3
Bank: 0 Reg: 0x0243d048 Val: 0x00000055 → spi3_sck_py0
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 → spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 → spi1_mosi_pz5
Bank: 0 Reg: 0x0243d060 Val: 0x00000055 → spi3_mosi_py2
Bank: 0 Reg: 0x0243d068 Val: 0x00000414 → cv_pwr_req_px1
Bank: 0 Reg: 0x0243d070 Val: 0x00000400 → uart2_tx_px4
Bank: 0 Reg: 0x0243d078 Val: 0x00000450 → uart2_rx_px5
Bank: 0 Reg: 0x0243d080 Val: 0x00000408 → uart2_rts_px6
Bank: 0 Reg: 0x0243d088 Val: 0x00000458 → uart2_cts_px7
Bank: 0 Reg: 0x0243d090 Val: 0x00000415 → uart5_rx_py6
Bank: 0 Reg: 0x0243d098 Val: 0x00000051 → uart5_tx_py5
Bank: 0 Reg: 0x0243d0a0 Val: 0x00000051 → uart5_rts_py7
Bank: 0 Reg: 0x0243d0a8 Val: 0x00000415 → uart5_cts_pz0
Bank: 0 Reg: 0x0243d0b0 Val: 0x00000059 → usb_vbus_en0_pz1
Bank: 0 Reg: 0x0243d0b8 Val: 0x00000415 → usb_vbus_en1_pz2
Bank: 0 Reg: 0x02441000 Val: 0x00022415 → ufs0_rst_pff1
Bank: 0 Reg: 0x02441008 Val: 0x00022415 → ufs0_ref_clk_pff0

Checking with devmem2:
sudo devmem2 0x0243d040

/dev/mem opened.
Memory mapped at address 0x7f925b5000.
Value at address 0x243D040 (0x7f925b5040): 0x444

sudo devmem2 0x0243d010

/dev/mem opened.
Memory mapped at address 0x7f85501000.
Value at address 0x243D010 (0x7f85501010): 0x448

sudo devmem2 0x0243d020

/dev/mem opened.
Memory mapped at address 0x7f88a9e000.
Value at address 0x243D020 (0x7f88a9e020): 0x444

sudo devmem2 0x0243d050

/dev/mem opened.
Memory mapped at address 0x7f943bd000.
Value at address 0x243D050 (0x7f943bd050): 0x448

sudo devmem2 0x0243d058

/dev/mem opened.
Memory mapped at address 0x7fb2220000.
Value at address 0x243D058 (0x7fb2220058): 0x444

Those REG is correct. Could you check the loopback test to verify it.

I have connected pins 19 and 21 together and ran ./spidev_test -v and got the following output:

sudo ./spidev_test -v
can’t open device: No such file or directory
Aborted

I have checked in /dev/ and there is no spi device.
After running sudo modprobe spidev I get the following output for lsmod | grep -i spi:

spidev 13282 0

But ls -l /dev/spi* gives the following output:

ls: cannot access ‘/dev/spi*’: No such file or directory

You need below context for spidev driver.

	spi@3210000 {
		compatible = "nvidia,tegra186-spi";
		reg = <0x0 0x3210000 0x0 0x10000>;
		interrupts = <0x0 0x24 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		iommus = <0x2 0x20>;
		dma-coherent;
		dmas = <0x19 0xf 0x19 0xf>;
		dma-names = "rx", "tx";
		spi-max-frequency = <0x3dfd240>;
		nvidia,clk-parents = "pll_p", "clk_m";
		clocks = <0x4 0x87 0x4 0x66 0x4 0xe>;
		clock-names = "spi", "pll_p", "clk_m";
		resets = <0x5 0x5b>;
		reset-names = "spi";
		status = "okay";
		linux,phandle = <0xf2>;
		phandle = <0xf2>;

		spi@0 {
			compatible = "spidev";
			reg = <0x0>;
			spi-max-frequency = <0x2faf080>;

			controller-data {
				nvidia,enable-hw-based-cs;
				nvidia,rx-clk-tap-delay = <0x10>;
				nvidia,tx-clk-tap-delay = <0x0>;
			};
		};

		spi@1 {
			compatible = "spidev";
			reg = <0x1>;
			spi-max-frequency = <0x2faf080>;

			controller-data {
				nvidia,enable-hw-based-cs;
				nvidia,rx-clk-tap-delay = <0x10>;
				nvidia,tx-clk-tap-delay = <0x0>;
			};
		};
	};


	spi@3230000 {
		compatible = "nvidia,tegra186-spi-slave";
		reg = <0x0 0x3230000 0x0 0x10000>;
		interrupts = <0x0 0x26 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		iommus = <0x2 0x20>;
		dma-coherent;
		dmas = <0x19 0x11 0x19 0x11>;
		dma-names = "rx", "tx";
		spi-max-frequency = <0x3dfd240>;
		nvidia,clk-parents = "pll_p", "clk_m";
		clocks = <0x4 0x89 0x4 0x66 0x4 0xe>;
		clock-names = "spi", "pll_p", "clk_m";
		resets = <0x5 0x5d>;
		reset-names = "spi";
		status = "okay";
		linux,phandle = <0xf4>;
		phandle = <0xf4>;

		spi@0 {
			compatible = "spidev";
			reg = <0x0>;
			spi-max-frequency = <0x2faf080>;

			controller-data {
				nvidia,enable-hw-based-cs;
				nvidia,rx-clk-tap-delay = <0x10>;
				nvidia,tx-clk-tap-delay = <0x0>;
			};
		};

		spi@1 {
			compatible = "spidev";
			reg = <0x1>;
			spi-max-frequency = <0x2faf080>;

			controller-data {
				nvidia,enable-hw-based-cs;
				nvidia,rx-clk-tap-delay = <0x10>;
				nvidia,tx-clk-tap-delay = <0x0>;
			};
		};
	};

Thanks! I have applied those changes and now everything works! I have both I2C and SPI.
I have checked both with spidev-test and with my SPI device, it’s all fine.

So to sum-up:

  • I flashed the default OS freshly downloaded from the Nvidia website on a new SD card
  • started the Jetson Xavier NX dev kit and configured it for both SPI and i2c using jetson-io
  • copied the generated dtb file on a USB drive and stopped the Xavier NX
  • booted the Xavier NX with my custom OS
  • copied the dtb file from the USB drive to the home directory
  • decompiled the dtb file with sudo dtc -I dtb -O dts -o file.dtb decompiled.dts
  • edited the file to replace the “compatible” lines as explained by SchaneCCC in the message above
  • recompiled the dts file into a dtb file with sudo dtc -I dts -O dtb -o new_file.dtb decompiled.dts
  • copied the generated new_file.dtb to /boot/dtb
  • edited the /boot/extlinux/extlinux.conf file to change the FTD line in the JetsonIO part to point towards the new dtb file
  • rebooted

I had a strange issue where I couldn’t ssh into my Xavier NX after the reboot, but I un-plugged the power and plugged it again and the Xavier booted properly and now everything works.

Thanks for the help.

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