We made a Nano carrier board with two IMX174 imagers connected to SPI0.
To convert from Sony SubLVDS to CSI-2 we implemented a Crosslink FPGA for each of the two IMX174.
Furthermore there is one additional sensin
g device on the SPI bus.
So we have got a sum of 5 slaves at the SPI bus.
We used a SN74LVC138 1-of-8 decoder to expand SPI_CS0* ( pin 95 of Nano ) . The A, B, C - inputs of 74LVC138 are connected to GPIOs PC.04, PE.06 and PZ.00 .
We can communicate with all five SPI-bus slaves in user mode with a modified spidev_test.c using dev/spi/spidev0.0 where we set the GPIOs for the 74LVC138 according to our desired slave.
But when we insert a kernel module imx174.o on boot, we loose spidev0.0 an can no longer access the Crosslink FPGA in user mode.
So the question is: Can it be done in the device tree to define SPI-busses dev/spi/spidev0.0 through /dev/spidev/spidev0.4 an tell the system that these five busses need the setting of GPIOs PC.04, PE,.06 and PZ.00 in a well defined manner ?
spidev0.0 is spidev0 with PC.04=0, PE.06=0, PZ.00 = 0
spidev0.1 is spidev0 with PC.04=1, PE.06=0, PZ.00 = 0
spidev0.2 is spidev0 with PC.04=0, PE.06=1, PZ.00 = 0
spidev0.3 is spidev0 with PC.04=1, PE.06=1, PZ.00 = 0
spidev0.4 is spidev0 with PC.04=0, PE.06=0, PZ.00 = 1