Support for Multiple VC IDs on Single CSI Input with FPGA Aggregator + D3 16-Port FPD-Link Interface on Jetson Xavier

[shivlal12345]

Hello,

I’m using the Jetson Xavier (Tegra194) platform along with a custom FPGA aggregator that takes 3 camera inputs and outputs them via a single CSI-2 link using 3 distinct Virtual Channel IDs (VC IDs 0, 1, and 2).

This CSI stream is passed through a serializer into the D3 Engineering 16-port FPD-Link III interface board, which simply relays the serialized signal to the Jetson Xavier via FPD-Link and a deserializer (e.g., TI UB960).

On the Xavier side, this aggregated CSI stream enters via a single CSI port.

My goal is to configure the device tree so that all 3 VC ID streams can be captured independently — ideally exposed as separate /dev/videoX nodes, each via its own VI port.

Questions:

1. Does the Jetson Xavier (Tegra194) platform support demultiplexing multiple VC IDs over a single CSI-2 input into separate VI ports?
2. If not, are there any supported workarounds — such as ISP bypass mode, software demux, or custom driver paths?
3. Would this functionality be supported on Jetson AGX Orin or Orin NX instead?

[francis.guindon]

Hi @shivlal12345,

Your set up sounds quite fascinating. I looked into the Xavier TRM and found around page 618 that the Xavier series should handle multiple virtual channels per CSI port.

I also looked into some other resource that might help for your scenario … the closest I found is this guide for working with virtual channel and GMSL on AGX Xavier. While your set up is different, perhaps there is some information on working with virtual channel that you might find useful.

Regards,
Francis Guindon

Embedded SW Engineer at RidgeRun
Contact us: support@ridgerun.com
Developers wiki: https://developer.ridgerun.com/
Website: http://www.ridgerun.com/

[ShaneCCC]

Yes, it’s supported by Xavier/Orin.

Thanks