Hi ,
We are currently designing a custom carrier board for the Jetson AGX Thor T5000 SOM and reviewing the high-speed I/O (UPHY) allocation.
We would like to inquire about the usage and multiplexing capabilities of UPHY_RX5 / UPHY_TX5 (UPHY Lane 5). Could you please help clarify the following questions:
- Availability: Is UPHY Lane 5 (UPHY_RX5 / UPHY_TX5) fully functional and supported on the Thor T5000 production SOM? Are there any hardware limitations or reserved states associated with this lane?
- Supported Functions: What specific high-speed protocols/functions can this lane be configured for? (e.g., PCIe controller/lane, USB 3.x Gen1/Gen2, 10G/1G Ethernet / QSGMII, etc.)
- HSIO Configuration Table: Which HSIO / UPHY configuration preset (or ODMDATA / Pinmux setting) enables and assigns UPHY Lane 5? Could you point us to the corresponding table/section in the Jetson Thor Design Guide or Pinmux Spreadsheet?
- Reference Clock Assignment: If configured for PCIe or other high-speed interfaces, which reference clock pair (REFCLK) is dedicated or recommended to be paired with UPHY Lane 5?
Any guidance, documentation references, or pinmux recommendations would be greatly appreciated.
Thank you for your time and assistance!