tegra_channel_error_status:error 22

Hi,

I am trying to develop a driver for a MIPI camera based on ov5693.c. I adopt the suggestions in https://devtalk.nvidia.com/default/topic/1049476/jetson-tx1/tx1-csi-without-i2c/4.

Hardware: TX1 with J120
Software: JetPack 3.3 with L4T R28.2

When I used the command

v4l2-ctl -d /dev/video0 --set-fmt-video=width=1280,height=720,pixelformat=YUYV --set-ctrl bypass_mode=0 --stream-mmap --stream-count=1 --stream-to=test.raw

I get the following errors

[  974.582642] vi 54080000.vi: tegra_channel_error_status:error 22 frame 0
[  974.668099] video4linux video0: frame start syncpt timeout!0
[  974.752066] video4linux video0: frame start syncpt timeout!0

I enable the dynamic debug with the following command

echo file vi2_fops.c +p > /sys/kernel/debug/dynamic_debug/control
echo file csi2_fops.c +p > /sys/kernel/debug/dynamic_debug/control

Now I get the following messages

[ 3224.958555] vi 54080000.vi: Calibrate csi port 4
[ 3225.055095] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 3225.061701] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000000
[ 3225.067376] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000000
[ 3225.073277] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.079480] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.085467] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 3225.092428] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.098592] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.104501] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 3225.125054] vi 54080000.vi: tegra_channel_error_status:error 22 frame 0
[ 3225.138108] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 3225.144498] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 3225.150133] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000060
[ 3225.155859] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.161984] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.167852] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 3225.184049] vi 54080000.vi: tegra_channel_error_status:error 22 frame 1
[ 3225.197102] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 3225.203485] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 3225.209092] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000060
[ 3225.214847] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.220970] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.226896] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 3225.243061] vi 54080000.vi: tegra_channel_error_status:error 22 frame 2
[ 3225.256142] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 3225.262527] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 3225.268131] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000060
[ 3225.273861] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.280014] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.285876] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 3225.302041] vi 54080000.vi: tegra_channel_error_status:error 22 frame 3
[ 3225.315118] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 3225.321504] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 3225.327155] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000060
[ 3225.332882] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.339028] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.344940] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 3225.361126] vi 54080000.vi: tegra_channel_error_status:error 22 frame 4
[ 3225.374209] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 3225.380603] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 3225.386212] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000060
[ 3225.391952] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.398083] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.403987] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 3225.420160] vi 54080000.vi: tegra_channel_error_status:error 22 frame 5
[ 3225.433222] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 3225.439639] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 3225.445241] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000060
[ 3225.450935] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.457024] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.462854] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 3225.478976] vi 54080000.vi: tegra_channel_error_status:error 22 frame 6
[ 3225.491953] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 3225.498302] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 3225.503898] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000060
[ 3225.509592] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.515681] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.521511] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 3225.537630] vi 54080000.vi: tegra_channel_error_status:error 22 frame 7
[ 3225.550606] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 3225.556955] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 3225.562525] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000060
[ 3225.568239] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.574331] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.580158] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 3225.596280] vi 54080000.vi: tegra_channel_error_status:error 22 frame 8
[ 3225.609255] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 3225.615608] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000000
[ 3225.621177] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000060
[ 3225.626867] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.632984] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.638815] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 3225.744568] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 3225.750935] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 3225.756570] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000060
[ 3225.762280] vi 54080000.vi: cil_settingtime is pulled from device
[ 3225.768393] vi 54080000.vi: cil_settingtime was autocalculated
[ 3225.774230] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10

What do these messages mean? And what is the possible reason for the errors?

Thank you!

It’s could be the signal didn’t match MIPI spec.
Please have a reference to the TRM to get REG CSI_CSI_CILA_STATUS_0 statement.

TEGRA_CSI_CILX_STATUS 0x00000060

I power down the MIPI camera and repeat the experiment. Now I get

[  193.236738] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000000
[  193.242306] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000000

which is different from the results above. Can I get the conclusion that when the MIPI camera is powered on, the MIPI hardware in TX1 receive signals, but TX1 can not detect the signal because it think that the signal didn’t match MIPI spec( CIL-A detects LP state 01 or 10 followed by a stop state LP11 instead of transitioning)? I want to make sure that I set the correct port number for MIPI in the device tree.

According to https://devtalk.nvidia.com/default/topic/1049476/jetson-tx1/tx1-csi-without-i2c/3, some parameters are very important: num_lanes, tegra_sinterface, discontinuous_clk,dpcm_enable, cil_settletime, active_w, active_h, pixel_t, readout_orientation, mclk_multiplier, pix_clk_hz, csi-port, bus-width, mode_type, csi_pixel_bit_depth, pixel_phase. Which of them are related to the error “TEGRA_CSI_CILX_STATUS 0x00000060”?

Thank you!

I believe these two discontinuous_clk, cil_settletime should be most relative.

How to set the parameter cil_settletime? For example, I want to set it to 120 ns. Set

cil_settletime = "120"

in the device tree?

Have a check the TRM the REG “CSI_PHY_CILB_CONTROL0_0”

CILB_THS_SETTLE: Settle time for data lane when moving from LP to HS (LP11->LP01-
>LP00), this setting determines how many CSICIL clock cycles (102 MHz LP clock cycles)
to wait, after LP00, before starting to look at the data.
0xF is an illegal value for this field.
85ns + 6 * UI < (Ths-settle-programmed + 5) * csicil_clk_period < 145ns + 10 * UI

Now I get the following error message

[  121.259424] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[  121.266271] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[  121.272940] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000000
[  121.278743] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000000
[  121.284630] vi 54080000.vi: cil_settingtime is pulled from device
[  121.290921] vi 54080000.vi: cil_settingtime was autocalculated
[  121.296934] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[  121.303838] vi 54080000.vi: cil_settingtime is pulled from device
[  121.309939] vi 54080000.vi: cil_settingtime was autocalculated
[  121.315769] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[  121.322649] LT8918: ov5693_s_stream starts.
[  121.326835] video4linux video0: tegra_channel_capture_frame: vi2 got SOF syncpt buf[ffffffc06f926000]
[  121.336086] video4linux video0: tegra_channel_release_frame: vi2 got EOF syncpt buf[ffffffc06f926000]
[  121.413194] video4linux video0: frame start syncpt timeout!0
[  121.418862] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[  121.425220] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00004000
[  121.431572] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000003
[  121.437149] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000031
[  121.442841] vi 54080000.vi: cil_settingtime is pulled from device
[  121.448932] vi 54080000.vi: cil_settingtime was autocalculated
[  121.454761] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[  121.461650] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[  121.467999] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[  121.474491] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000000
[  121.480130] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000000
[  121.485903] vi 54080000.vi: cil_settingtime is pulled from device
[  121.492055] vi 54080000.vi: cil_settingtime was autocalculated
[  121.497890] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[  121.504772] video4linux video0: tegra_channel_capture_frame: vi2 got SOF syncpt buf[ffffffc06f925c00]
[  121.514028] video4linux video0: tegra_channel_release_frame: vi2 got EOF syncpt buf[ffffffc06f925c00]
[  121.593222] video4linux video0: frame start syncpt timeout!0
[  121.598920] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[  121.605301] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[  121.611676] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000002
[  121.617283] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000021
[  121.622988] vi 54080000.vi: cil_settingtime is pulled from device
[  121.629084] vi 54080000.vi: cil_settingtime was autocalculated
[  121.634918] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10

Now TEGRA_CSI_CILX_STATUS becomes 0x00000021. According to CSI_CSI_CILA_STATUS_0, it means “Control Error. Set when CIL-A detects incorrect line state sequence on clk lane”. What is the possible reason for this error?

The TEGRA_CSI_PIXEL_PARSER_STATUS show package head have error.

HPA_UNC_HDR_ERR: Uncorrectable Header Error. Set when header parser A parses a header with a
multi-bit error. This error will be detected by the headers ECC, but cannot be corrected. The packet will be
discarded.

Hi xu.wang,

Have you managed to get issue resolved? Any result can be shared?

Thanks

No, I am still working on this problem. Maybe some of the error messages are related to the hardware of the MIPI camera, and I am discussing it with the vendor. Your comment on discontinuous_clk and cil_settletime has helped me a lot.