Nano 2gb + 2 max9296 + 4 max9295 + gw5300isp + 4 imx490

Can I use Nano 2GB to connect two channels max9296, each channel max9296 to two channels max9295, each channel max9295 to one IMX490 with ISP?
One max9296 is connected to CSI0 and CSI1 of nano 2GB, and the other max9296 is connected to CSI2 and CSI3 of Nano 2GB.



The first is a wiring diagram of nano 2GB, and the second is a wiring diagram of 9296。
Since nano2GB’s CSI0 /1/2/3 are 2 pairs of Lane, each MAX9296 portA and portB connects only 2 pairs of Lane to a CSIx of nano2GB.
The output image format of each IMX490 camera is 2880*1860@30fps YUV422-8bit.

When I run the v4l2-ctl command, the following error occurs: video4linux video0: frame start syncpt timeout!0
How do I troubleshoot the problem?
dmesg_log.txt (63.8 KB)
imx490.c (49.5 KB)
imx490_mode_tbls.h (11.1 KB)
tegra210-camera-rbpcv2-imx490.dtsi (28.8 KB)
tegra210-porg-camera-rbpcv2-imx490.dtsi (4.0 KB)

After I use this command: echo 7 >/sys/class/video4linux/video0/dev_debug I then use the v4l2-ctl --set-fmt-video=width=2880,height=1680,pixelformat=YUYV --set-ctrl bypass_mode=0 --stream-mmap --stream-count=100 -d /dev/video0 --stream-to=ov491.raw command and generate a new log
dmesg_log1.txt (7.3 KB)

Enable the debug print in csi2_fops.c to check the error log to analysys.

hi ShaneCCC
When I want to Enable the debug print in csi2_fops.c, the following error occurs
nvidia@nvidia-desktop:~$ sudo chmod 777 /sys/kernel/debug/dynamic_debug/control
[sudo] password for nvidia:
nvidia@nvidia-desktop:~$ sudo echo file csi2_fops.c +p > /sys/kernel/debug/dynamic_debug/control
-bash: /sys/kernel/debug/dynamic_debug/control: Permission denied

Check below command.

sudo su
echo file csi2_fops.c +p > /sys/kernel/debug/dynamic_debug/control

hi ShaneCCC

nvidia@nvidia-desktop:~$ sudo su
root@nvidia-desktop:/home/nvidia# echo file csi2_fops.c +p > /sys/kernel/debug/dynamic_debug/control
root@nvidia-desktop:/home/nvidia# dmesg

[ 784.370250] vi 54080000.vi: Calibrate csi port 2
[ 784.371614] vi 54080000.vi: Calibrate csi port 1
[ 784.390736] vi 54080000.vi: cil_settingtime was autocalculated
[ 784.390743] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 784.594871] video4linux video1: frame start syncpt timeout!0
[ 784.601079] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 784.601098] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 784.601114] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 784.601231] vi 54080000.vi: cil_settingtime was autocalculated
[ 784.601250] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 784.802712] video4linux video1: frame start syncpt timeout!0
[ 784.808925] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 784.808944] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 784.808959] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 784.809089] vi 54080000.vi: cil_settingtime was autocalculated
[ 784.809108] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 785.010838] video4linux video1: frame start syncpt timeout!0
[ 785.017043] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 785.017062] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 785.017077] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 785.017197] vi 54080000.vi: cil_settingtime was autocalculated
[ 785.017216] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 785.218644] video4linux video1: frame start syncpt timeout!0
[ 785.224844] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 785.224863] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 785.224879] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 785.224999] vi 54080000.vi: cil_settingtime was autocalculated
[ 785.225018] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 785.426745] video4linux video1: frame start syncpt timeout!0
[ 785.432948] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 785.432968] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 785.432984] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 785.433112] vi 54080000.vi: cil_settingtime was autocalculated
[ 785.433131] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 785.634784] video4linux video1: frame start syncpt timeout!0
[ 785.640987] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 785.641007] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 785.641023] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 785.641147] vi 54080000.vi: cil_settingtime was autocalculated
[ 785.641166] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 785.842382] video4linux video1: frame start syncpt timeout!0
[ 785.848726] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 785.848739] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 785.848750] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 785.848840] vi 54080000.vi: cil_settingtime was autocalculated
[ 785.848853] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 786.050811] video4linux video1: frame start syncpt timeout!0
[ 786.057047] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 786.057066] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 786.057083] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 786.057201] vi 54080000.vi: cil_settingtime was autocalculated
[ 786.057220] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 786.258755] video4linux video1: frame start syncpt timeout!0
[ 786.264959] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 786.264978] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 786.264994] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 786.265122] vi 54080000.vi: cil_settingtime was autocalculated
[ 786.265141] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 786.466698] video4linux video1: frame start syncpt timeout!0
[ 786.472905] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 786.472923] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 786.472938] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 786.473064] vi 54080000.vi: cil_settingtime was autocalculated
[ 786.473083] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 786.674717] video4linux video1: frame start syncpt timeout!0
[ 786.681025] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 786.681045] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 786.681060] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 786.681195] vi 54080000.vi: cil_settingtime was autocalculated
[ 786.681215] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 786.882673] video4linux video1: frame start syncpt timeout!0
[ 786.888871] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 786.888891] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 786.888908] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 786.889034] vi 54080000.vi: cil_settingtime was autocalculated
[ 786.889053] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 787.091081] video4linux video1: frame start syncpt timeout!0
[ 787.097280] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 787.097333] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 787.097381] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 787.097573] vi 54080000.vi: cil_settingtime was autocalculated
[ 787.097594] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 787.298249] video4linux video1: frame start syncpt timeout!0
[ 787.303967] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 787.303973] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 787.303979] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 787.304031] vi 54080000.vi: cil_settingtime was autocalculated
[ 787.304038] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 787.506702] video4linux video1: frame start syncpt timeout!0
[ 787.512782] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 787.512836] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 787.512881] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 787.513094] vi 54080000.vi: cil_settingtime was autocalculated
[ 787.513147] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 787.714770] video4linux video1: frame start syncpt timeout!0
[ 787.720794] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 787.720847] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 787.720893] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 787.721107] vi 54080000.vi: cil_settingtime was autocalculated
[ 787.721159] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 787.922712] video4linux video1: frame start syncpt timeout!0
[ 787.928700] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 787.928752] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 787.928799] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 787.929491] vi 54080000.vi: cil_settingtime was autocalculated
[ 787.929516] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
root@nvidia-desktop:/home/nvidia#

Looks like signal problem. Have check the REG CSIx_CSI_CILA_STATUS_0 from TRM to get more information.

CILA_CTRL_ERR: Control Error. Set when CIL-A detects LP state 01 or 10 followed by a stop state (LP11)
instead of transitioning into the Escape mode or Turn Around mode (LP00).

Hi ShaneCCC
What is TRM? is Tegra_x1_TRM ? where is Tegra_x1_TRM

?
You mean, I look at CSI2_CSI_CILA_STATUS_0 in TRM? How should I check this reg value ?

I refer to this document, and I get confused.

I want to debug a camera first.
This camera is connected to the nano’s CSI2 via the max9296 portA


the csi2 is 2 lanes
In my dtsi configuration

port-index = <2>;
bus-width = <2>;
tegra_sinterface = “serial_c”;

Is this the right configuration?

[tegra210-camera-rbpcv2-imx490.dtsi|attachment](upload://uqQc4oKDqlAb91uDkE6Vjrc6yVl.dtsi) (28.8 KB)

tegra210-camera-rbpcv2-imx490.dtsi (28.8 KB)

The port-index/bus-width … in device tree is correct.
TRM can download from download center. Tegra X1 SoC Technical Reference Manual

vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040040
0x00040040 == 0b0100 0000 0000 0100 0000
This message shows that Bit 6 and Bit 18 is set to 1 .
What should I do next?

[ 113.837690] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010


0x00000010 == 0b00010000
This message shows that Bit 4 is set to 1 . means CILA_CTRL_ERR

[ 113.837737] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040040
This message shows CILA_DATA_LANE1_CTRL_ERR and CILA_DATA_LANE0_CTRL_ERR

Hi Shane
Is there any way to check whether the MIPI data of MAX9296 is normally transmitted to the CSI interface of nano?

Sorry, may need to check with scope to make sure the signal.

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.