- Currently using the Jetson_Linux_R36.4.3_aarch64 version, with hardware being the AGX Orin 64G version.
- Currently, we are using the LT6911UXE chip to transmit 3840*2160@60 YUV422 format data to CSI-C/CSI-D, with each lane having a bandwidth of 2.45G.
- The following error occurs when retrieving the transmitted data.The image output has abnormalities.
[ 128.924141] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 1, flags: 0, err_data 4194402
[ 136.524400] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 1, flags: 0, err_data 6291554
[ 136.641298] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 1, flags: 0, err_data 6291554
[ 138.559085] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 1, flags: 0, err_data 64
[ 139.926215] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 1, flags: 0, err_data 64 - When I lower the input frame rate to 3840*2160@55fps, there are no errors, and the image is normal.
- When testing with input frame rates from 55fps to 60fps, errors and image abnormalities occur above 56fps.
- What configurations are required on the Orin platform to achieve a MIPI bandwidth of 2.5G?
- Currently using DPHY, could the bandwidth limitation to 2.2G be caused by deskew issues?
dts
i2c@c250000 {
status = "okay";
6911a@2b {
compatible = "nvidia,lt6911uxe";
status = "okay";
reg = <0x2b>;
devnode = "video1";
/* Interrupt */
interrupt-parent = <&gpio>;
interrupts = <&gpio TEGRA234_MAIN_GPIO(AC,7) IRQ_TYPE_LEVEL_HIGH>;
sensor_model = "p3785";
reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AC,5) GPIO_ACTIVE_HIGH>;
mode0 { // E2832_3840x2160
mclk_khz = "24000";
num_lanes = "4";
tegra_sinterface = "serial_c";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "3840";
active_h = "2160";
mode_type = "yuv";
pixel_phase = "uyvy";
csi_pixel_bit_depth = "16";
readout_orientation = "0";
line_length = "4400";
inherent_gain = "1";
mclk_multiplier = "24";
pix_clk_hz = "594000000";
};
mode1 { // E2832_1920x1080_60Fps
mclk_khz = "24000";
num_lanes = "4";
tegra_sinterface = "serial_c";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1920";
active_h = "1080";
mode_type = "yuv";
pixel_phase = "uyvy";
csi_pixel_bit_depth = "16";
readout_orientation = "0";
line_length = "2200";
inherent_gain = "1";
mclk_multiplier = "24";
pix_clk_hz = "594000000";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
p3785_out1: endpoint {
status = "okay";
port-index = <2>;
bus-width = <4>;
remote-endpoint = <&p3785_csi_in1>;
};
};
};
};
};
channel@1 {
reg = <1>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
p3785_csi_in1: endpoint@2 {
port-index = <2>;
bus-width = <4>;
remote-endpoint = <&p3785_out1>;
};
};
port@1 {
reg = <1>;
p3785_csi_out1: endpoint@3 {
status = "okay";
remote-endpoint = <&p3785_vi_in1>;
};
};
};
};
tegra-capture-vi {
nvidia,vi-mapping =
<0 1>,
<1 1>,
<2 1>,
<3 1>,
<4 0>,
<5 0>;
num-channels = <2>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
status = "okay";
p3785_vi_in0: endpoint {
status = "okay";
port-index = <4>;
bus-width = <8>;
remote-endpoint = <&p3785_csi_out0>;
};
};
port@1 {
reg = <1>;
status = "okay";
p3785_vi_in1: endpoint {
status = "okay";
port-index = <2>;
bus-width = <4>;
remote-endpoint = <&p3785_csi_out1>;
};
};
};
};
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* max_pixel_rate = <>;
* Max pixel rate in Kpixel/s for the ISP ISO case
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <4>;
max_lane_speed = <5000000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <1500000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
/**
* The general guideline for naming badge_info contains 3 parts, and is as follows,
* The first part is the camera_board_id for the module; if the module is in a FFD
* platform, then use the platform name for this part.
* The second part contains the position of the module, ex. "rear" or "front".
* The third part contains the last 6 characters of a part number which is found
* in the module's specsheet from the vender.
*/
modules {
module0 {
status = "okay";
badge = "p3785_ltx6911-1";
position = "bottomleft";
orientation = "1";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
status = "okay";
/* Declare the device-tree hierarchy to driver instance */
sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/i2c@0/6911e@2b";
};
};
module1 {
status = "okay";
badge = "p3785_ltx6911-2";
position = "bottomright";
orientation = "1";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
status = "okay";
/* Declare the device-tree hierarchy to driver instance */
sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@c250000/i2c@0/6911a@2b";
};
};
};
};
[ 2041.140802] [RCE] ERROR: camera-ip/nvcsi/nvcsi.c:2015 [nvcsi_stream_set_config] "MIPI clock rate not known. Using 250000 kHz
[ 2041.140815] [RCE] "
[ 2041.159852] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 1, flags: 0, err_data 4194402
[ 2041.293214] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 1, flags: 0, err_data 4194402
While acquiring data, there are RCE errors. Could it be an issue with the RCE causing incorrect clock settings, making it unable to achieve 2.5G bandwidth data acquisition?
The MIPI clock rate is depend on pix_clk_hz.
Please print the MIPI rate in the csi5_fops.c to confirm.