Understood and thank you for the reply. To restate the question: What is the effective thermal resistance between the case and the TTP (θcp)?
The Thermal Design Document v1.1 states a thermal resistance θjp =0.35 to 0.65C depending on load balance, and we are in the process of dressing such balance. In our application we have also implemented our own thermal solution, which interfaces directly with the SOC case/top rather than Nvidia’s TTP. In our design, the SoC case is an intermediate point along θjp, with θjp = θjc + θcp. We define θcp as a the fixed nominal resistance between the case of the SoC and the TTP. In our design we have a similar thermal interface approach at the SoC and we intend to calculate θjc = θjp - θcp, with the variable aspect of your published θjp associated θjc followed by a fixed θcp.
Can you please define an effective θcp? Where θcp is part of the Nvidia design and not part of our design. For this you can assume that our design spreads the heat along the interface at top of the SoC case equivalently to the Nvidia design.
As far as direct measurements go, it would be quite difficult for us to directly measure the top of the case without disturbing this very critical thermal interface without rendering the measurement invalid. Perhaps you have access to test or simulation data that characterizes θcp, which is rather fixed and perhaps simpler to measure, so we can back it out of the design and de-embed θjc. Alternately, if you do have θjc, or an alternate definition of θjc, please provide it as this would be greatly appreciated.