Hi Nvidia
We have referenced the Design Guide to design the timing for SW Shutdown using the MCU. Please help verify if it is correct.
The VDD_3V3/VDD_1V8 Power Good signal is controlled by CARRIER_POWER_ON.
Unfortunately, we are not able to review or verify individual custom carrier board designs, including timing diagrams, on the forum. Please check your design against the SW shutdown sequence and timing requirements in the Jetson Thor Series Modules Design Guide. The Schematic Checklist in the Design Guide and the Jetson AGX Thor Developer Kit carrier board (P4071) schematics are also useful references.
If something in the Design Guide is unclear, such as a specific timing parameter or a signal requirement, please let us know which part, and we will be happy to help clarify it.
If you see an actual problem on your board, such as an unexpected reset during SW shutdown, please share the measured waveforms (for example SHUTDOWN_REQ*, POWER_EN, SYS_RESET*, and CARRIER_POWER_ON) along with a short description. We can then look into it further.
Our question is about a possible conflict between the SW shutdown timing and the HW reset timing.
The first step in the SW shutdown sequence is Sys_Reset_N being pulled low — but that is also the trigger condition for a HW reset. As a result, we are seeing the MCU stuck in the SW shutdown sequence after a HW reset, waiting for Carrier_Power_ON to be pulled low. Since this is a reset sequence, Carrier_Power_ON never gets pulled low.
How does NVIDIA prevent this on your side?