在DG文档的下电时序中,需要把SYS_RESET_N拉低,文档中显示该管脚是双向管脚,那么这个下电时序图中SYS_RESET_N是thor芯片拉低的还是mcu拉低的?恕我直言,此处文档应补充说明该信号由谁控制。
Since there is a timing requirement between the MODULE_POWER_ON input and the SYS_RESET_N bidirectional signal, the source of the MODULE_POWER_ON (presumably an MCU on the carrier) should also assert SYS_RESET_N from the carrier side within the required 0~25us period.
但是在button mcu (EFM8SB10F2G) 的固件代码中没有看到对SYS_RESET_N (P1.1) 的控制输出操作
SYS_RESET is in an input to the Button MCU, not an output.
So who controls the output SYS_RESET_N pin in carrier?
As per Jetson Thor Series Modules Interface Design Guide, the power sequencer drives it and the carrier board can optionally drive it:
This is a poor design; a single pin should not be ambiguous.
The SYS_RESET_N is bidirectional and open-drain, so it allows for multiple sources to assert reset. The power sequencer on the module releases the reset during boot. The carrier board may hold it low until ready, then release it — or it can simply leave it released (not assert at all) if no delay is needed.
carrier board 如何判断reset何时被power sequencer释放呢?


