TK1 DSI to FPGA

Hi all.

We made a custom board based on TK1.
We connect the DSI_A to the FPGA,then FPGA to HDMI-TX .

such as:
DSI_A_CLK_N >> FPGA
DSI_A_CLK_P >> FPGA
DSI_A_D0_N >> FPGA
DSI_A_D0_P >> FPGA
DSI_A_D1_N >> FPGA —> HDMI-TX --> HDMI(DVI) monitor display
DSI_A_D1_P >> FPGA
DSI_A_D2_N >> FPGA
DSI_A_D2_P >> FPGA
DSI_A_D3_N >> FPGA
DSI_A_D3_P >> FPGA

the problem:
1. monitor light is on but the screen is black(no signal) .
2. Is this DSI waveform correct?
2-1. DSI_A_D0_P
https://drive.google.com/drive/folders/0BxmJEALb7dhlNGpIcnZNWTdIeHc
2-2. DSI_A_CLK_P
https://drive.google.com/drive/folders/0BxmJEALb7dhlbmZ0YUJUUnhMMEU

Thanks

this is my Step

Step 1: set arch/arm/boot/dts/tegra124-soc.dtsi:
host1x{
:
dc@54200000 {
:
};
dsi@54300000 {
compatible = “nvidia,tegra124-dsi”;
reg = <0x54300000 0x00040000>;
nvidia,dsi-controller-vs = <1>;
status = “okay”;

	  /*panel-s-wqxga-10-1 {   
		//Documentation/devicetree/bindings/video/nvidia,tegra124-dsi.txt
			:
	  }*/
};

}

Step 2: set fb0 (we use busybox ,not X11)
/boot/extlinux/extlinux.conf
–> fbcon=map:0

Step 3: probe waveform

  1. DSI_A_D0_P
  2. DSI_A_CLK_P

Can you extend the waveform and list clk and data waveform in same screenshot? It only looks roughly correct…

Hi Trumany.
thank you for your reply

this is new waveform

red: data_0_p
yellow: clock_p
screen: white pattern

https://drive.google.com/drive/folders/0BxmJEALb7dhlalE4cWtQRjlsZWM

Looks like normal signal.Basically if you follow the DG to design your board, and keep the layout request of DSI part of DG, there should no problem of signal quality.

Did you use DSI panel to verify?

Hi Trumany.
thank you for your reply.

We did not use the panel to verify.
DSI directly connected to the FPGA.

How does DSI connect to the mipi-panel?
Is it directly connected?

ex:
DSI_A_CLK_N pin <-> mipi-panel pin
DSI_A_CLK_P pin <-> mipi-panel pin
DSI_A_D0_N pin <-> mipi-panel pin
DSI_A_D0_P pin <-> mipi-panel pin

First you need a DSI LCD panel and then follow its instruction to connect each signal.

Basically DSI port of TK1 is verified before ship out, and if your board design totally follow the design guide, there will be no hardware issue.
Since you use FPGA to convert DSI to HDMI, the most possible risk is your driver for conversion.

BTW, TK1 also support HDMI output, why you still try converting DSI to HDMI?

Hi Trumany.
thank you for your reply.

We measured HS mode.
The swing is 400 mV.
this is waveform
https://drive.google.com/drive/folders/0BxmJEALb7dhld1BEdkhkQ0I3alE

There is a description in the manual(NVIDIA JETSON TX1 MIPI DSI/CSI DESIGN AND TUNING)
:
/**
* If the swing is 400mV(0V to 400mV),the receiver is not terminating the bus.
* Check that the receiver side (NVIDIA®Tegra®for CSI and the LCD for DSI)
* is programmed properly and ready to accept input.
**/

  1. Does this mean that the receiver is not ready yet?

  2. Is it possible that the transmission side is not set correctly ?
    ex: Phy timing,Video mode …

  3. Devmem2 can not read and write to the registers (which causes the system to crash).
    All host1x sub-devices (ex: dc, dsi, csi …) can not be accessed. Why ?
    thanks.

Yes, i think your receiver side has no correct terminating, this should be the one of root causes.

For devmem2, are you using the doc of TX1? You need to find the correct address of registers in TK1’s TRM.

Hi Trumany.
thank you for your reply.
We have solved the problem of the swing(0~400mv) of the receiver(FPGA)
Now, DSI receiver (FPGA) can receive signals from TK1.

TK1 DSI output default is 1920X1200, we want to change to 1920x1080

We modify arch/arm/mach-tegra/panel-p-wuxga-10-1.c

static struct tegra_dc_mode dsi_p_wuxga_10_1_modes[] = {

	{
	   /*
		.pclk = 154700000,
		.h_ref_to_sync = 4,
		.v_ref_to_sync = 1,
		.h_sync_width = 16,
		.v_sync_width = 2,
		.h_back_porch = 32,
		.v_back_porch = 16,
		.h_active = 1920,
		.v_active = 1200,
		.h_front_porch = 120,
		.v_front_porch = 17,
	     */

	 	/* change */
		.pclk =			148500000,
		.h_ref_to_sync =	4,
		.v_ref_to_sync =	1,
		.h_sync_width =		44,	/* hsync_len */
		.v_sync_width =		5,	/* vsync_len */
		.h_back_porch =		148,	/* left_margin */
		.v_back_porch =		36,	/* upper_margin */
		.h_active =		1920,	/* xres */
		.v_active =		1080,	/* yres */
		.h_front_porch =	88,	/* right_margin */
		.v_front_porch =	4,	/* lower_margin */
	
	},
};
static struct tegra_dsi_out dsi_p_wuxga_10_1_pdata = {
						:
	--- .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
	+++ .pixel_format = TEGRA_DSI_PIXEL_FORMAT_16BIT_P,

	--- .video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_TX_ONLY,
	+++ .video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS,

	--- .pkt_seq = panasonic_1920_1200_vnb_syne,
	+++ .pkt_seq = NULL /*use  dsi_pkt_seq_video_non_burst_syne*/,
};

Q1: Are there any parts that need to be modified?

Q2: What is h_ref_to_sync & v_ref_to_sync?

thanks…

Hi Jinyo,

Q1: Are there any parts that need to be modified?
-> If you could boot the display without other errors, no other pars needed.

Q2: What is h_ref_to_sync & v_ref_to_sync?
->h_ref_to_sync and v_ref_to_sync are values internal to the architecture of NVIDIA display controllers and is not part of the final output signal. Please try 4 and 1 first.

For question 2, we have constraints about the value.

Please take a look at

kernel/display/drivers/video/tegra/dc

with function calc_h_ref_to_sync and calc_v_ref_to_sync

Hi ! WayneWWW,
thank you for your reply.

We decode the DSI signal and convert it into Vsync, Hsync, DE.

We think that Hsync should always be triggered, even if it is not in the active area
We found that the Hsync signal appears to follow the DE signal.

this is wareform:
https://drive.google.com/drive/folders/0BxmJEALb7dhlbnN0NmhNMkVpa1E

Q1. What is the reason for this?

Q2. How does the Hsync signal always be triggered?
Are there any other parameters that can be modified?

Thanks…

Hi Jinyo,

Could you try to control the h_sync_width to see if the Hsync signal also changed?

Why do you need to make Hsync always trigger?

Hi ! WayneWWW,
thank you for your reply.

Our resolution is 1080P60,
According to CEA (Consumer Electronics Association) -861B standards.
Hsync should always keep the trigger.

ex:
https://www.google.com.tw/search?biw=1920&bih=947&tbm=isch&sa=1&q=CEA-861B+Hsync+1080&oq=CEA-861B+Hsync+1080&gs_l=psy-ab.3...5847.7147.0.7397.5.5.0.0.0.0.42.186.5.5.0....0...1.1.64.psy-ab..0.0.0.s-tsyvuxJXo#imgrc=aiHu-h7y3JJHuM:

Thanks…

Hi Jinyo,

Have you lit your panel? Are there any other error messages except the HS signal looking weird?

Hi ! WayneWWW,
thank you for your reply.

Our panel no signal

We found a register field.
DC_DISP_H_PULSEx_CONTROL_0

Bit: 7 ~ 6
H_PULSE2_V_QUAL: H Pulse 2 Vertical Qualifier
0 = always running
2 = run during vertical active area
3 = run during vertical active plus 1 line

Bit: 4
H_PULSE2_POLARITY: H Pulse 2 Polarity. Polarity adjustment is done before the vertical
Qualifier is applied
0 = HIGH
1 = LOW

Q1:
H Pulse {0,1,2} Vertical Qualifier
If set to 0 (always running), will Hsync keep the trigger?

Q2:
H_PULSE2_POLARITY:
Is it Video signal sync polarity?

thanks …

Hi Jinyo,

Our panel no signal -> Could you share the kernel log by command “dmesg” ?

Hi ! WayneWWW,
thank you for your reply.

Our panel not DSI panel

We connect the DSI_A to the FPGA,then FPGA to our HDMI-TX .
HDMI-TX to display monitor .

this is dmesg :

when init:

dmesg | grep “tegradc”

[ 0.457708] platform tegradc.0: IOVA linear map 0xf8500000(1200000)
[ 0.461022] platform tegradc.0: IOVA linear map 0xf9700000(4800000)

[ 1.291741] tegradc tegradc.0: DSI: HS clock rate is 297000
[ 1.573228] tegradc tegradc.0: nominal-pclk:148500000 parent:148500000 div:1.0 pclk:148500000 147015000~161865000
[ 1.662496] tegradc tegradc.0: DSI pad calibration done
[ 1.666565] tegradc tegradc.0: probed
[ 1.667268] tegradc tegradc.0: nominal-pclk:148500000 parent:297000000 div:2.0 pclk:148500000 147015000~161865000
[ 1.709126] tegradc tegradc.0: fb registered

when I click keyboard:

~ # [ 64.468791] p,wuxga-10-1 panel dt support not available
[ 64.748109] tegradc tegradc.0: nominal-pclk:5000000 parent:10000000 div:2.0 pclk:5000000 4950000~5450000
[ 64.838516] tegradc tegradc.0: DSI pad calibration done

thanks …

Hi ! WayneWWW
I am gary on behalf of Jinyo to explain the DSI problem we encountered.
please see the attach word file in detail.
thanks for your teach.

gary zheng

Hi ! WayneWWW
I am gary on behalf of Jinyo to explain the DSI problem we encountered.
please see the attach word file in detail.
thanks for your teach.

gary zheng