TX1 Custom Carrier Device Tree

Autonomous Machines Jetson & Embedded Systems Jetson TX1
1

Hello,
I’m having difficulty getting a device tree to work for a custom carrier board. The pin mapping is below. I’ve read the adaptation guide but there are a few things that are not clear to me there.

  1. The USB lane mapping chart uses "0", "1" etc. differently between TX1 pins and the "Use Case" rows.
  2. The "lane-map" is not clearly documented (at least not in this doc).

Any help is appreciated.

Pin	Jetson TX1 Name	Tegra X1 Name	Physical Port
------------------------------------------------------
B43	USB2_D-		USB3_DN		USB 2 Port
B42	USB2_D+		USB3_DP
------------------------------------------------------
B40	USB0_D-		USB0_DN		USB 3 Port 0
B39	USB0_D+		USB0_DP
F44	USB_SS0_RX-	PEX_RX5N
F43	USB_SS0_RX+	PEX_RX5P
C44	USB_SS0_TX-	PEX_TX5N
C43	USB_SS0_TX+	PEX_TX5P
------------------------------------------------------
A39	USB1_D-		USB2_DN		USB 3 Port 1
A38	USB1_D+		USB2_DP
G43	USB_SS1_RX-	PEX_RX3N
G42	USB_SS1_RX+	PEX_RX3P
D43	USB_SS1_TX-	PEX_TX3N
D42	USB_SS1_TX+	PEX_TX3P
------------------------------------------------------
C49	PEX0_RST#	PEX_L0_RST_N	Ethernet Chip (82574L)
A45	PEX0_REFCLK-	PEX_CLK1N
A44	PEX0_REFCLK+	PEX_CLK1P
H45	PEX0_RX-	PEX_RX4N
H44	PEX0_RX+	PEX_RX4P
E45	PEX0_TX-	PEX_TX4N
E44	PEX0_TX+	PEX_TX4P
2

Hi trpropst,

The USB lane mapping chart uses “0”, “1” etc. differently between TX1 pins and the “Use Case” rows.
Could you point out where is the “USB lane mapping chart” and the “Use Case” rows?

According to “22.7 USB PADCTL” of https://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual, lane p5 and lane p3 can be used usb port 1 and 2 respectively. The information you provided seems incorrect.

3

Could you point out where is the “USB lane mapping chart” and the “Use Case” rows?

I’m referring to the table in the “USB lane mapping” section of the “PLATFORM ADAPTATION AND
BRING-UP GUIDE”. This document is included in the driver package documents. The same table is in the OEM product design guide (table 12 in that document).

The information you provided seems incorrect.

The information in the table I provided was copied from the OEM product design guide, table 86. The “Physical Port” column of my table is the connector on our carrier board where we are routing the TX1 pins. Everything else is from the OEM guide. This is where the confusion starts for us. Where we see USB_SS0 on pins F44/43, C44/43, it is not clear if that is “Port 0” in the table you refer to in the TRM (Lane 6) or “USB_SS0” in the OEM guide (Lane 5). Table 86 seems to clearly call those pins lane 5 (and port 0).

Thanks for the help on this.

4

To clarify, the Platform Adaptation Guide is in the L4T R24.2 Documentation package at http://developer.nvidia.com/embedded/dlc/l4t-documentation-24-2. Within that download, you will find the PDF, document DA_07839-001_01, under the “baggage” directory.

One fundamental question is how to modify the device tree for use-case 4 as defined there. The example given calls out a value for the lane-map of 0x11 however also shows it as 0x12 in the pcie_controller section.

5

We will review the info in the table and update it if incorrect.

6

For use case 4, because PCIe is 2x1, please configure it as 0x11.

7

Using 0x11 in both places caused the system to not boot. Changing it to 0x11 in the xusb section and 0x21 in the pcie-controller section (as stated in the guide) was the only way to make it work.

What is the distinction between the two lane-map values?