TX1: MIPI-CSI2 BT.656 suffix

This is a BT.656 format question for MIPI-CSI2 in TX1.
・ Which of the video data superimposed on MIPI_CSI2 is BT.656-3 or BT.656-4?
・ Can it be changed by setting?

that’s all.

No sure if my understanding is correct. The BT.656 is different protocol with the MIPI. The BT.656 may need a bridge to convert to MIPI signal to CSI interface.

Below link may help on this.

https://devtalk.nvidia.com/default/topic/1051481/jetson-tx2/tx2-with-jetpack4-2-mipi-csi-video-quality-issue/2

Hi. ShineCCC

Thank you for your reply.

I think MIPI-CSI2 is an image of the BT.656 physical layer converted to differential serial.

The exact IC we are using is the ADV7280A-M, with a setting of -3 / -4. (Currently set to ‘-3’)
I was able to import images, but I was wondering if the current settings were correct.
I wanted to know the specifications of the MIPI-CSI2 video input section of Jetson_TX1.
If you know the specification of Tegra_X1, please give me information.

This is an additional question.
The 507i NTSC signal is deinterlaced with the ADV7280-M and the 507p video is input. However, there is a problem with the image quality, and we are examining whether or not it can be expanded in memory without interlacing.
Is it possible to capture ODD field / EVEN field in 1 frame or 2 frames?

Best regard.

  1. For the format support you may get more detail information from the TRM VI chapter.(VIDEO INPUT)
  2. I don’t thin Tegra can support the ODD/EVEN filed in 1 frame or 2 frames. But can support if the ODD/EVEN size is the same.

Hi. ShineCCC.

  1. For the format support you may get more detail information from the TRM VI chapter.(VIDEO INPUT)

Tegra_X1_TRM: I read Chapter 31, but the word “BT.656” did not appear.
Refer to TRM.

  1. I don’t thin Tegra can support the ODD/EVEN filed in 1 frame or 2 frames. But can support if the ODD/EVEN size is the same.

You say you can do it?
The rest depends on the device tree, right?

That’s all.

As I said BT.656 doesn’t matter with MIPI so that should not appear in MIPI spec and TRM.
I would like to say tegra can support it if the ODD/EVEN size it the same but I don’t have any experience for it.