Hello, anyone can help to confirm the TX1 exposed USB2.0 port mapping with USB controller in chip?
Right now there are 3 USB port exposed (USB0/USB2/USB3).
It looks USB0 (Pin B39/B40) should be mapped to USB2.0 controller #1 becuase it is OTG;
questions are aboyut USB2(Pin #A38/A39)/USB3 (PinB42/B43) , another possibility is they are both mapped to USB2.0 controller #2, but USB2.0 controller #2 only has HSIC port (from X1 datasheet) .
So it looks for me there are two possibilities:
TX1 USB2/USB3 are mapped to USB2.0 controller #1 as well (on carrier board they just simply dispatched to a Standard A port)
TX1 USB2/USB3 are mapped to USB2.0 controller #2, that means one on-module USB PHY chip must be used.
Anyone from Nvidia can help to confirm?