TX1 USB2/USB3 port vs. USB controller

Hello, anyone can help to confirm the TX1 exposed USB2.0 port mapping with USB controller in chip?
Right now there are 3 USB port exposed (USB0/USB2/USB3).
It looks USB0 (Pin B39/B40) should be mapped to USB2.0 controller #1 becuase it is OTG;

questions are aboyut USB2(Pin #A38/A39)/USB3 (PinB42/B43) , another possibility is they are both mapped to USB2.0 controller #2, but USB2.0 controller #2 only has HSIC port (from X1 datasheet) .

So it looks for me there are two possibilities:

  1. TX1 USB2/USB3 are mapped to USB2.0 controller #1 as well (on carrier board they just simply dispatched to a Standard A port)

  2. TX1 USB2/USB3 are mapped to USB2.0 controller #2, that means one on-module USB PHY chip must be used.

Anyone from Nvidia can help to confirm?

USB2 and USB3 are both mapped to XUSB controller, not USB2.0 controller. XUSB controller provides mechanisms to communicate with USB2.0 peripherals.

@Trumany or that is out of my expectation – USB2 and USB3 both under XUSB controller.

Thanks for the quick reply!

@Trumany one more question, the USB1 port, which is not exposed but internally connected with WIFI on module, that is also under XUSB controller?

To be more precise, if USB1/2/3 are all under XUSB 2.0 controller, they shall have separate datapath with XUSB 3.0 controller?

USB1/2/3 are different ports but share one same controller. You can get details in chapter 22 of TRM.