TX2 MIPI CSI ECC bug

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
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1

Hi everyone,
I use TX2 MIPI CSI recieve camera image data, I set camera senenor output error ECC in packet header, when set bit7 and bit6 ECC error TX2 can not detect error, when set any bit of bit5:0 TX2 can detect ECC error and recieve image timeout . The MIPI CSI reciever can correct 1 bit ECC and detect 2 bits ECC. How to fix thi issue? Thank.

3

Try to disable the ecc check by programing the REG NVCSI_STREAM_0_INTR_MASK_0 and NVCSI_STREAM_0_ERR_INTR_MASK_0 also NVCSI_STREAM_0_ERROR_STATUS2VI_MASK_0

1 Like
4

Hi ShaneCCC,

I shoud use ECC check. I mean t when TX2 recieve bit7 or bit6 ECC error TX2 do not detect the error, How to fix the issuse?

5

TX2 support CSI-2 v1.3, in CSI-2 v1.3 spec, the ECC are only 6 bits,

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Thank you for your reply.