Nvcsi -- CRC errors

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

Hello All,

The test setup is: FPGA board → Nvidia Jetson Tx2 board.

Here, csi-port: 0 and lanes: 4.
Able to receive the CSI2 packets.

In Phy level, Getting the errors in 3rd and 4th data lanes as: sot multi bit error, sot single bit and control errors. Got these errors in sometimes and not getting in sometimes.

In stream level, Getting the CRC errors.

Able to print the Packet Header DI (Data type) and Word Count.

The log is:

[ 139.059632] nvcsi 150c0000.nvcsi: csi4_stream_check_status(0) ERROR_STATUS2VI_VC1 = 0x00000004
[ 139.068345] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x00000040
[ 139.076191] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x00000040
[ 139.084385] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) PH_DI_0 0x0000005e
[ 139.091882] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) PH_WC_0 0x0f400f40
[ 139.099388] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) PF_CRC_0 0xddfa405e
[ 139.106971] nvcsi 150c0000.nvcsi: csi4_cil_check_status (0) CILB_INTR_STATUS 0x000001da
[ 139.115000] nvcsi 150c0000.nvcsi: csi4_cil_check_status (0) CILB_ERR_INTR_STATUS 0x000001da

How to solve this problem.

-Thanks.

2

Apply the patch from below link to disable the ECC check to try.

https://elinux.org/Jetson_TX2_Camera_BringUp

3

Hi ShaneCCC,

In CSI2 Tx, CRC, the generator polynomial is x16+x12+x5+x0

What about the Nvidia CSI Rx?

-Thanks.

4

Hi ShaneCCC,

Thanks for the patch.
I am able to find out the problem using this.

Now I am able to see the video in Tx2 board.

-Thanks.