TX2 USB Lane Mapping configs #4

JasonFan · January 29, 2018, 12:02pm

Hi WayneWWW,

Thanks for your patient.

Config#2: PCIe#0_0 okay, USB_SS#0 okay. but I need another USB3. (default pcie set 4x1, 1x1)
So I consider to config#4 in the beginning.

config#3: PCIe is gone. USB_SS#1 and USB_SS#2 are okay.

Config#4: PCIe is gone. USB_SS#0, USB_SS#2 okay. (Our custom board only has two USB3 connectors)

So I think USB may not be a problem now. I can use config#3 for USB_SS#1 and USB_SS#2.
or config#4 fot USB_SS#0, USB_SS#2.

For USB configuration between config#3 and Config#4. I only choose usb3-1 and usb3-2 for config#3
Or usb3-0 and usb3-2 for config#4 because there are only two usb3-std-A-port can be modified.
Config#3

pinctrl@3520000 {
	    pinmux {
		usb3-std-A-port2 {
			<b>nvidia,lanes = "usb3-1";</b>
			nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
			status = "okay";
		};
		usb3-std-A-port3 {
			nvidia,lanes = "usb3-2";
			nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
			status = "okay";
		};
		e3325-usb3-std-A-HS {
                    status = "okay"; //This is usb2.0 port on M.2
		};
	};
      };

pci@3,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};

pcie0_lane2_mux {
			status = "okay";
		};

Config#4

pinctrl@3520000 {
	    pinmux {
		usb3-std-A-port2 {
			<b>nvidia,lanes = "usb3-0";</b>
			nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
			status = "okay";
		};
		usb3-std-A-port3 {
			nvidia,lanes = "usb3-2";
			nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
			status = "okay";
		};
		e3325-usb3-std-A-HS {
                    status = "okay"; //This is usb2.0 port on M.2
		};
	};
      };

pci@3,0 {
			nvidia,num-lanes = <1>;
			status = "disabled";
		};

pcie0_lane2_mux {
			status = "disabled";
		};

For PCIe issue,
Once I config Pcie to 1x1x1 (check log, it indeed set to 1x1, 1x1, 1x1), no matter the status of pci@3,0 is set to okay or disabled, lspci can’t see anything.
By my previous test, PCie onle can detected by setting 4x1, 1x1 or 2x1, 1x1, 1x1.

WayneWWW · January 29, 2018, 2:16pm

Hi JasonFan,

2x1,1x1,1x1 → Does it mean config #5? Under such case, your PCIe can work but and only one USB can work?

WayneWWW · January 29, 2018, 2:28pm

BTW, usb3-std-A-port, this naming can be an arbitrary string. If you want to enable all three usbs, just add one more node with the “nvidia,lanes = “usb3-x”;” and set status to “okay”. (x = the remaining usb you didn’t use)

But you only has 2 usb port on carrier board, so I think you cannot verify it.

JasonFan · January 30, 2018, 4:11am

Hi WayneWWW,

2x1,1x1,1x1 → Does it mean config #5? Under such case, your PCIe can work but and only one USB can work?

----> I didn’t set ODMDATA to config#5. During previous test (ODMDATA=0x7090000), I just try to set different PCie lane number and found this phenomenon. For default pcie setting is 4x1 0 1x1, if I set pcie wrong, system will set to 2x1, 1x1, 1x1. Under these two cases, PCIe can work and only one USB can work.

So maybe we can focus on pcie problem. why to set 1x1 1x1 1x1, PCie can’t work.

Attachment is log and dtsi files

Thanks again.
0130.7z (32.2 KB)

JasonFan · January 30, 2018, 4:42am

Hi WayneWWW,

Base on Config#3

I change Pcie setting to

pcie-controller@10003000 {
		pci@1,0 {
			nvidia,num-lanes = <2>;
			nvidia,disable-clock-request;
			status = "okay";
		};
		pci@2,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
		pci@3,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
	};

And now PCIe#0_0, USB_SS#2, USB_SS#1 can work now.
It looks like there is not consistency between document and drivers.

I’ll keep trying config$4

WayneWWW · January 30, 2018, 4:44am

It looks like your PCIe only works when USB_SS1 pin is configured to PCIe#0_1.

If so, your pcie should work under config#1,#2,#5,$6.

Could you confirm this assumption first?

WayneWWW · January 30, 2018, 4:51am

Yes, your latest try really make things interesting…

That one looks like a config#5, but behavior looks like #6…

JasonFan · January 30, 2018, 8:28am

Hi WayneWWW,

Base on

pcie-controller@10003000 {
		pci@1,0 {
			nvidia,num-lanes = <2>;
			nvidia,disable-clock-request;
			status = "okay";
		};
		pci@2,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
		pci@3,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
	};

Set USB to “usb3-0”, “usb3-2”, PCIe#0_0, USB_SS#0, USB_SS#2 are okay.

If set pci@3,0 to disabled, PCIe#0_0, USB_SS#0 are okay but USB_SS#2 can’t work.

I think that’s why I felt confused before.

I’ll use these two configurations and continue to work. Thanks a lot for your great help.

WayneWWW · January 30, 2018, 9:33am

I am glad to hear that. Did you change your hardware before?

Feel like your USB_SS#X is not the same order as adaptation guide.

JasonFan · January 30, 2018, 9:57am

Hi WayneWWW,

I have checked USB_SS#X with our HW engineer. It is the same design to Jetson TX2.
According to my previous test, I think the order of USB_SS#X should be no problem.
I was confused that even PCIe to be set 1x1 1x1 1x1, our pcie device should be detected.
But only PCIe is set to 4x1, 1x1 or 2x1, 1x1, 1x1, it can work well.

Once I have new discovery, I’ll share it here.

Thanks again.

qiumincooltuf2p · June 2, 2018, 10:08am

Hi WayneWWW,
I confused with similary problem as JasonFan met.Our situation like this:

we use B40,B39(USB0_N && USB0_P) as micro usb2.0
use A38(USB1_P) A39 F43(USB_SS0_RX_P) F44 C43 C44 as Type A usb3.0 port 1
use B42(USB2_P) B43 G42 G43 D42 D43 as Type A usb3.0 port 2

I try to comment out overwrite codes in plugin-manager and modify our tegra186-quill-p3310-1000-a00-00-base.dts as below. ODMDATA is correct. Then both two type A usb have no volt on them, and because of this I can’t put my dmesg to here. The kernel source version used is R27.1.
Please check it for me, thank you!

usb_cd {
		status = "okay";
		phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>;
		phy-names = "otg-phy";
	};

	xudc@3550000 {
		status = "okay";
		phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
		phy-names = "usb2", "usb3";
		emc-frequency = <150000000>;
	};
	
	pcie-controller@10003000 {
		status = "okay";
		pci@1,0 {
			nvidia,num-lanes = <1>;
			nvidia,disable-clock-request;
			status = "okay";
		};
		pci@2,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
		pci@3,0 {
			nvidia,num-lanes = <1>;
			status = "disabled";
		};
	};
	xhci@3530000 {
		status = "okay";
		phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(2)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
		phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-2", "usb3-0";
	};

	pinctrl@3520000 {
		    status = "okay";
		    pinctrl-0 = <&tegra_xusb_padctl_pinmux_default>;
		    pinctrl-names = "default";
		    tegra_xusb_padctl_pinmux_default: pinmux {
                usb2-micro {
                    nvidia,lanes = "otg-0";
                    nvidia,function = "xusb";
                    nvidia,port-cap = <TEGRA_PADCTL_PORT_OTG_CAP>;
                };
                usb2-1 {
                    nvidia,lanes = "otg-1";
                    nvidia,function = "xusb";
                    nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
                };
                usb2-2 {
                    nvidia,lanes = "otg-2";
                    nvidia,function = "xusb";
                    nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
                };
                usb3-1 {
                    nvidia,lanes = "usb3-0";
                    nvidia,function = "xusb";
                    nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
                };
                usb3-2 {
                    nvidia,lanes = "usb3-2";
                    nvidia,function = "xusb";
                    nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
                };
            }; 
	};

	gpio@2200000 {
		sdmmc-wake-support-input {
			status = "okay";
		};

		sdmmc-wake-support-output {
            status = "okay";
        };

		pcie0_lane2_mux {
			status = "disabled";
		};
	};

tegra186-quill-p3310-1000-a00-00-base.dts.txt (5.83 KB)
tegra186-quill-p3310-1000-a00-plugin-manager.dtsi.txt (6.55 KB)

WayneWWW · June 4, 2018, 5:52am

Are you configuring one 3.0 port as OTG port?

Also, do you set status of usb3-1 and usb3-2 to “okay”?

qiumincooltuf2p · June 5, 2018, 1:30am

Hi WayneWWW,
Do you mean I need to configure at least one usb3.0 port as OTG port?

And I need to add ''' status = "okay" ''' in usb3-1{ }  block?

Thanks for reply

Devin

WayneWWW · June 6, 2018, 6:56am

Do you mean I need to configure at least one usb3.0 port as OTG port?
→ Yes, because I see you add usb3 to xudc.

And I need to add ‘’’ status = “okay” ‘’’ in usb3-1{ } block?
->Yes, please also refer to Jetson/TX2 USB - eLinux.org