Following the NVIDIA Jetson AGX Xavier PCIe Endpoint Design Guidelines (DA-09357) I’m referring to “Figure 1” shown below. We have x8 cable with reversed signals (TX of RC to RX of EP) and coupling capacitors connected. However, the control signals that go through Open Drain (denoted as “OD” in Figure) buffers need further clarifications.
One question is whether OD buffers are intended to invert the control signal at its input (aka active LOW logic)? Furthermore, the two back-to-back OD buffers at “CLKREQ” control signals, what is this circuit intended to do? Because if not controlled properly one could cause a short circuit from the VDD_3V3 signals to GND. Is it supposed to be some sort of state-maintaining logic?
Any further clarifications on this topic are welcome!
Buffers are required on the control signals to ensure that the module pins are not driven prematurely as the two devices are powered up, which may not be simultaneously. This is to avoid backdrive on the control signals.
Refer to Attachments section in the app note. Reference schematics is attached to the app note. OD buffers in the schematics are non inverting. And part number of OD buffer is provided in the schematics. You can download the OD buffer data sheet for further details. PEX_L5_CLKREQ_N is Input when Jetson AGX Xavier is Root Port and Output when Jetson AGX Xavier is Endpoint and hence two back to back connected OD buffers are used.
