JAO: PCIe RP EP

[liyutai]

Hi NV Support Team
We want to used two orin communction with PCIe, Reference “Jetson_AGX_Xavier_Series_PCIe_Endpoint_Design_Guidelines_DA-09357-001_v1.3”

e.g. in below figure 1. The left Xavier as root port and right Xavier as end port.
The “CLKREQ_N” used bidirection buffer, “RST” / “WAKE” use unidirection buffer.
My query: Why only “CLKREQ_N” need add Bidirectional buffer as show in below.
From my understanding if left Xavier as root port, that means CLKREQ_N is input for root port.
it is not bidirection if we have fixed RP selection. Is it correct?

[kayccc]

Please check Jetson AGX Orin Platform Adaptation and Bring-Up — Jetson Linux
Developer Guide 34.1 documentation (nvidia.com).
You can find the Bring up Tegra PCIe Endpoint Mode from there.

[liyutai]

So the CLKREQ_N is bidirection ?

[Trumany]

It depends on your use case, either Orin can be RP or EP. Better to follow the default suggested design/pinmux setting.

[liyutai]

Hi Trumany
When we used Orin is RP and M.2 is EP.
Because for clock request used EP to request RP to output reference clock. In this case for Orin it is input.
Do you think if we also need must config CLKREQ as bidirection in pinmux ?

Thanks
Yutai

[Trumany]

As said it depends on your use case.