I have a question about the PEX_x_CLKREQ_N pin type as described in the AGX Orin Design Guide.
When Jetson is RC, Table 7-16 shows it as input/output (I/O), but Table 7-18 shows it as input (I).
When Jetson is acting as an RC, I think this pin type is input, not bidirectional, is this correct?
Could someone please respond to me regarding this issue?
Yes, this pin is input as Root Port. But the pin type itself is I/O as it can be ouput as End Point. We’ll consider if need to change to Input in Table 7-16, thanks.
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