What is OD in E3317-A01 x16 PCIe Tx/Rx swap module

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
1

Hi,

I am trying to design a PCB board for two Xavier boards’ PCIe*8 communication based on the design in the document, NVIDIA JETSON AGX XAVIER PCIe ENDPOINT DESIGN GUIDELINES(attached to this post). I am a bit confused about the part connected to PEX CTRL as shown below.

Question:

  1. what is OD in the above figure? Why we need it?
  2. I am new to PCIe. I didn’t find a lot of information about PEX ctrl. Even not sure what it stands for. May I ask how this PEX ctrl works with PCIe*8 communication?

Thanks!
Jetson_AGX_Xavier_PCIe_Endpoint_Design_Guidelines.pdf (1.9 MB)

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2

OD means ‘open drain’, you can find the component in attachment in your paste pdf file. Its p/n is SN74AUP1G07, a single buffer gate with open drain output.

For hw design, only need to follow the guide to connect all PCIe lines. You can read PCIe spec for the detail control scheme if necessary.

3

Hi Trumany,

Thanks for your reply.

I have one last question. If I just need PCIe *8 communication, do I need the PEX ctrl connection between two Xavier boards?

Can I just have the connections between the pins that are circled as shown below?

Thank you!

4

No, please totally follow the guide.

5

Thanks!

I just found another problem. I was wondering whether I need 0.22uF capacitor between RX and TX as shown below:

Since in the E3317-A01 schematic, there is no capacitor between RX and TX as shown below:

Thanks!