[Xavier NX]TPM 2.0(Nuvoton_NPCT754AADYX) Bring Up

Dear All,

We’ve use jump-wired between SOM’s SPI0(SPI1 with CS0 in SFIO) and TPM’s EVK.
According vendor’s suggestion, the driver should use the tcg,tpm_tis_spi

But the driver seem always feedback some error such as below.

  1. error code that should indicates I/O error
...
[    4.446732] tpm tpm0: tpm_transmit: tpm_send: error -5
...
[    4.485235] tpm_tis_spi: probe of spi0.0 failed with error -5

Xavier_spi0_TPM_20220516_1356.log (235.0 KB)

  1. System will response connection timeout(-110) while tpm_tis_read8 that caused the tpm_tis_core_init result is ‘No such device’(-19)
[    4.614081] [lanner_tpm][tpm_tis_read8:115]
[    4.614180] [lanner_tpm][tpm_tis_spi_read_bytes:146]
[    4.614279] [lanner_tpm][tpm_tis_spi_transfer:68]
[    4.618674] [lanner_tpm][wait_startup:51]rc=-110,TPM_ACCESS(1)=0x1000
[    4.621867] [lanner_tpm][tpm_tis_core_init:716]rc=-19

Xavier_spi0_TPM_20220518_1924.log (135.8 KB)

However, the driver seems couldn’t bring up successful.
There’re my setting below so far.

Pinctrl register

root@lanner-desktop:~# cat /sys/kernel/debug/tegra_pinctrl_reg | grep spi
Bank: 1 Reg: 0x0c302028 Val: 0x00000002 -> spi2_mosi_pcc2
Bank: 1 Reg: 0x0c302038 Val: 0x00000002 -> spi2_cs0_pcc3
Bank: 1 Reg: 0x0c302048 Val: 0x00000002 -> spi2_sck_pcc0
Bank: 1 Reg: 0x0c302050 Val: 0x00000002 -> spi2_miso_pcc1
Bank: 0 Reg: 0x0243b000 Val: 0x00023440 -> qspi0_io3_pc5
Bank: 0 Reg: 0x0243b008 Val: 0x00023440 -> qspi0_io2_pc4
Bank: 0 Reg: 0x0243b010 Val: 0x00023440 -> qspi0_io1_pc3
Bank: 0 Reg: 0x0243b018 Val: 0x00023440 -> qspi0_io0_pc2
Bank: 0 Reg: 0x0243b020 Val: 0x00023460 -> qspi0_sck_pc0
Bank: 0 Reg: 0x0243b028 Val: 0x00023400 -> qspi0_cs_n_pc1
Bank: 0 Reg: 0x0243b030 Val: 0x00023415 -> qspi1_io3_pd3
Bank: 0 Reg: 0x0243b038 Val: 0x00023415 -> qspi1_io2_pd2
Bank: 0 Reg: 0x0243b040 Val: 0x00023415 -> qspi1_io1_pd1
Bank: 0 Reg: 0x0243b048 Val: 0x00023415 -> qspi1_io0_pd0
Bank: 0 Reg: 0x0243b050 Val: 0x00023435 -> qspi1_sck_pc6
Bank: 0 Reg: 0x0243b058 Val: 0x00023415 -> qspi1_cs_n_pc7
Bank: 0 Reg: 0x0243b060 Val: 0x00002000 -> qspi_comp
Bank: 0 Reg: 0x0243d008 Val: 0x00000415 -> spi3_miso_py1
Bank: 0 Reg: 0x0243d010 Val: 0x00000400 -> spi1_cs0_pz6
Bank: 0 Reg: 0x0243d018 Val: 0x00000415 -> spi3_cs0_py3
Bank: 0 Reg: 0x0243d020 Val: 0x00000450 -> spi1_miso_pz4
Bank: 0 Reg: 0x0243d028 Val: 0x00000415 -> spi3_cs1_py4
Bank: 0 Reg: 0x0243d040 Val: 0x00000440 -> spi1_sck_pz3
Bank: 0 Reg: 0x0243d048 Val: 0x00000415 -> spi3_sck_py0
Bank: 0 Reg: 0x0243d050 Val: 0x00000059 -> spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000400 -> spi1_mosi_pz5
Bank: 0 Reg: 0x0243d060 Val: 0x00000415 -> spi3_mosi_py2

Device Tree that refer How to enable TPM2.0 module in Xavier?

		spi@0 {
			compatible = "tcg,tpm_tis_spi";
			status = "okay";
			reg = <0x0>;
			#address-cells = <1>;
			#size-cells = <0>;
			spi-max-frequency = <50000000>;
//			spi-max-frequency = <5000000>;
			controller-data {
				nvidia,enable-hw-based-cs;
//				nvidia,cs-setup-clk-count = <0x1e>;
//				nvidia,cs-hold-clk-count = <0x1e>;
//				nvidia,rx-clk-tap-delay = <0x1f>;
//				nvidia,tx-clk-tap-delay = <0x0>;
//				nvidia,cs-inactive-cycles = <0x6>;
				nvidia,variable-length-transfer;
			};
		};

tegra194-p3668-common.dtsi (12.4 KB)
Does any one mind to help us to check our setting wrong or not first?

Best Regards,
MOMO Chen

Using jetson-io to configure the pins.

Bank: 1 Reg: 0x0c302028 Val: 0x00001002 -> spi2_mosi_pcc2
Bank: 1 Reg: 0x0c302038 Val: 0x00001002 -> spi2_cs0_pcc3
Bank: 1 Reg: 0x0c302048 Val: 0x00001002 -> spi2_sck_pcc0
Bank: 1 Reg: 0x0c302050 Val: 0x00001002 -> spi2_miso_pcc1
Bank: 0 Reg: 0x0243b000 Val: 0x00023440 -> qspi0_io3_pc5
Bank: 0 Reg: 0x0243b008 Val: 0x00023440 -> qspi0_io2_pc4
Bank: 0 Reg: 0x0243b010 Val: 0x00023440 -> qspi0_io1_pc3
Bank: 0 Reg: 0x0243b018 Val: 0x00023440 -> qspi0_io0_pc2
Bank: 0 Reg: 0x0243b020 Val: 0x00023460 -> qspi0_sck_pc0
Bank: 0 Reg: 0x0243b028 Val: 0x00023400 -> qspi0_cs_n_pc1
Bank: 0 Reg: 0x0243b030 Val: 0x00023415 -> qspi1_io3_pd3
Bank: 0 Reg: 0x0243b038 Val: 0x00023415 -> qspi1_io2_pd2
Bank: 0 Reg: 0x0243b040 Val: 0x00023415 -> qspi1_io1_pd1
Bank: 0 Reg: 0x0243b048 Val: 0x00023415 -> qspi1_io0_pd0
Bank: 0 Reg: 0x0243b050 Val: 0x00023435 -> qspi1_sck_pc6
Bank: 0 Reg: 0x0243b058 Val: 0x00023415 -> qspi1_cs_n_pc7
Bank: 0 Reg: 0x0243b060 Val: 0x00002000 -> qspi_comp
Bank: 0 Reg: 0x0243d008 Val: 0x00001444 -> spi3_miso_py1
Bank: 0 Reg: 0x0243d010 Val: 0x00001448 -> spi1_cs0_pz6
Bank: 0 Reg: 0x0243d018 Val: 0x00001448 -> spi3_cs0_py3
Bank: 0 Reg: 0x0243d020 Val: 0x00001444 -> spi1_miso_pz4
Bank: 0 Reg: 0x0243d028 Val: 0x00001448 -> spi3_cs1_py4
Bank: 0 Reg: 0x0243d040 Val: 0x00001444 -> spi1_sck_pz3
Bank: 0 Reg: 0x0243d048 Val: 0x00001444 -> spi3_sck_py0
Bank: 0 Reg: 0x0243d050 Val: 0x00001448 -> spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00001444 -> spi1_mosi_pz5
Bank: 0 Reg: 0x0243d060 Val: 0x00001444 -> spi3_mosi_py2

Dear Shane,

I’ve tune our pinmux config then flash it to SOM. but it seems no improved.
Xavier_spi0_TPM_20220520_0954_pinrctrl_tune.log (122.2 KB)
The log include
‘dmesg’
‘cat /sys/kernel/debug/tegra_pinctrl_reg’
‘dmesg | grep tpm’

[    4.095401] [lanner_tpm][tpm_tis_read8:115]
[    4.099595] [lanner_tpm][tpm_tis_spi_read_bytes:146]
[    4.104595] [lanner_tpm][tpm_tis_spi_transfer:68]
[    4.114259] [lanner_tpm][wait_startup:51]rc=-110,TPM_ACCESS(1)=0x1000
[    4.115706] [lanner_tpm][tpm_tis_core_init:718]rc=-19

Best Regards,
MOMO Chen

Can you confirm the SPI lookback test to confirm the configure.

Dear Shane,

Actually, We’ve been validate the SPI0 loopbcak by our supplier’ suggestion(with our pinctrl_reg before).
The MOSI is short to the MISO directly. But, we’re validate the loopback with the spidev,.
NOT the TPM driver(tpm_tis_spi).

DTS

        spi@3210000{ /* SPI1 in 40 pin conn */
                status = "okay";
                nvidia,clock-always-on;

                spi@0 { /* chip select 0 */
                        compatible = "spidev";
                        reg = <0x0>;
                        spi-max-frequency = <50000000>;
                        controller-data {
                                nvidia,enable-hw-based-cs;
                                nvidia,rx-clk-tap-delay = <0x10>;
                                nvidia,tx-clk-tap-delay = <0x0>;
                        };
                };
//              spi@0 {
//                      compatible = "tcg,tpm_tis_spi";
//                      status = "okay";
//                      reg = <0x0>;
//                      #address-cells = <1>;
//                      #size-cells = <0>;
//                      spi-max-frequency = <50000000>;
//                      spi-max-frequency = <5000000>;
//                      controller-data {
//                              nvidia,enable-hw-based-cs;
//                              nvidia,cs-setup-clk-count = <0x1e>;
//                              nvidia,cs-hold-clk-count = <0x1e>;
//                              nvidia,rx-clk-tap-delay = <0x1f>;
//                              nvidia,tx-clk-tap-delay = <0x0>;
//                              nvidia,cs-inactive-cycles = <0x6>;
//                              nvidia,variable-length-transfer;
//                      };
                };

Then validate with spi_dev utility.
validate with the spi0.0 / 0.1 / 2.0 / 2.1


The SPI0 has loopback with short MOSI and MISO
Then SPI2 Not.
*Sorry we’re only keep the photo so far.

We’re still curious “Is there any argument could add to DTS that possible to improve or not”, Because the tpm driver seems stuck with the kind of self test function at beginning.

/* Before we attempt to access the TPM we must see that the valid bit is set.
 * The specification says that this bit is 0 at reset and remains 0 until the
 * 'TPM has gone through its self test and initialization and has established
 * correct values in the other bits.'
 */
static int wait_startup(struct tpm_chip *chip, int l)
{

Best Regards,
MOMO Chen

Does this TPM device need power/reset control?
If don’t need enable power/reset may be can try remove the TPM driver and access by spidev_test to check if able communicate with it to clarify if HW or driver problem.

Dear Shane,

According our Hardware Engineer reply. it doesn’t need the power/reset.
I think that might be driver problem probably.

First, we need to sync with you. When we use the TPM driver(tpm_tis_spi).
Those log and signal that I just type as below with remote ssh.

rmmod tpm_tis_spi
rmmod tpm_tis_core
rmmod tpm
sleep 3
modprobe tpm_tis_spi

It will show up the error code -5

[ 1780.007505] tpm tpm0: tpm_transmit: tpm_send: error -5
...
[ 1780.041913] tpm_tis_spi: probe of spi0.0 failed with error -5

Then there is the signal( fetch with Zaleae logica 16) when driver insert.


As the photo show, the SOM seems no clock when we use the driver.
I’m already to reduce the adjust but compatible.
The result seems same.

                spi@0 { /* chip select 0 */
//                      compatible = "spidev";
                        compatible = "tcg,tpm_tis_spi";
                        reg = <0x0>;
                        spi-max-frequency = <50000000>;
                        controller-data {
                                nvidia,enable-hw-based-cs;
                                nvidia,rx-clk-tap-delay = <0x10>;
                                nvidia,tx-clk-tap-delay = <0x0>;
                        };
                };

tegra194-p3668-common.dtsi (12.5 KB)

===============================================
Add the spidev’s log and signal for reference, the signal is fetch with the command below.

./spidev_test -D /dev/spidev0.0 -v

Xavier_spi0_spidev_20220524_1144.log (681 Bytes)


Best Regards,
MOMO Chen

Dear Shane,

There is always no clock when we use the TPM driver(tpm_tis_spi).
Is there any suggestion for that?

Best Regards,
MOMO Chen

Could you remove TPM module to probe to clarify if TPM module pull the clock down.

Dear Shane,

We’ve validate the signal without TPM module. But it seems still no clock so far.


Is that expected??

Best Regards,
MOMO Chen

Dear Shane,

Update again, we’ve use the DevKit for the same signal verify without TPM module.
But the clock is still no signal so far.

  • We’re use the pure DevKit Image that only choice the tpm driver to spi.
  • Our supplier has verify with the same configuration(dts/pinmux) with the AGX Xavier DevKit, but there is the signal from spi clock.

I’ve also tried to access spi’s register for analysis/compare further, but it will cause the kernel panic with the ‘devmem2’ or ‘busybox devmem’, but it will cause the kernel panic.
I’ve been to use those utility to access usb’s register( for compliance) and successful.
Why those utility doesn’t suitable spi’s register?

# busybox devmem 0x03210000
0xDEAD2003
[  164.952480] CPU:0, Error:CBB-NOC@0x2300000,irq=478
[  164.952582] **************************************
[  164.952673] * For more Internal Decode Help
[  164.952756] *     http://nv/cbberr
[  164.952817] * NVIDIA userID is required to access
[  164.952899] **************************************
[  164.952986] CPU:0, Error:CBB-NOC
[  164.953050]  Error Logger            : 0
[  164.953122]  ErrLog0                 : 0x80030000
[  164.953190]    Transaction Type      : RD  - Read, Incrementing
[  164.953292]    Error Code            : SLV
[  164.953363]    Error Source          : Target
[  164.953435]    Error Description     : Target error detected by CBB slave
[  164.953557]    AXI2APB_3 bridge error: SFIFONE - Status FIFO Not Empty interrupt[  164.953685]        AXI2APB_3 bridge error: TIM - Timer(Timeout) interrupt
[  164.953800]    AXI2APB_4 bridge error: RDFIFOF - Read Response FIFO Full interruptroot@lanner-desktop:/sys/firmware/devicetree/base/spi@3210000/spi@0# [  164.954371]         Packet header Lock   : 0
[  164.955102]    Packet header Len1    : 3
[  164.955396]    NOC protocol version  : version >= 2.7
[  164.957392]  ErrLog1                 : 0x320020
[  164.960626]  ErrLog2                 : 0x0
[  164.963171]    RouteId               : 0x320020
[  164.966666]    InitFlow              : ccroc_p2ps/I/ccroc_p2ps
[  164.971396]    Targflow              : axis_satellite_grout/T/axis_satellite_grout
[  164.978041]    TargSubRange          : 0
[  164.981196]    SeqId                 : 0
[  164.984254]  ErrLog3                 : 0x3210000
[  164.987667]  ErrLog4                 : 0x0
[  164.990311]    Address               : 0x3210000 -- /spi@3210000 + 0x0
[  164.995978]  ErrLog5                 : 0x809f850
[  164.999306]    Non-Modify            : 0x1
[  165.002714]    AXI ID                : 0x10
[  165.005434]    Master ID             : CCPLEX
[  165.009104]    Security Group(GRPSEC): 0x7e
[  165.013303]    Cache                 : 0x0 -- Non-cacheable/Non-Bufferable)
[  165.019078]    Protection            : 0x2 -- Unprivileged, Non-Secure, Data Access
[  165.025905]    FALCONSEC             : 0x0
[  165.028965]    Virtual Queuing Channel(VQC): 0x0
[  165.033692]  **************************************
[  165.038319] kernel BUG at /home/lanner/workspace/nVIDIA/Jetson_Xavier_1.5.1_7814/officier_jetpack_4.6.1/Linux_for_Tegra/sources/kernel/nvidia/drivers/platform/tegra/tegra_cbb.c:839!
[  165.054433] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
[  165.059689] Modules linked in: fuse xt_conntrack ipt_MASQUERADE nf_nat_masquerade_ipv4 nf_conntrack_netlink nfnetlink xt_addrtype iptable_filter iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat nf_conntrack br_netfilter bnep zram overlay rtk_btusb btusb btrtl btbcm btintel userspace_alert rtl8822ce cfg80211 nvgpu ip_tables x_tables
[  165.092588] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.9.253 #2
[  165.098619] Hardware name: NVIDIA Jetson Xavier NX Developer Kit (DT)
[  165.104748] task: ffffff8009eb13c0 task.stack: ffffff8009ea0000
[  165.110792] PC is at tegra_cbb_error_isr+0x1a0/0x1a8
[  165.116031] LR is at tegra_cbb_error_isr+0xc8/0x1a8
[  165.120759] pc : [<ffffff8008cb3818>] lr : [<ffffff8008cb3740>] pstate: 604001c5
[  165.128627] sp : ffffffc1ffd02e50
[  165.131524] x29: ffffffc1ffd02e50 x28: 0000000000000005
[  165.137043] x27: 00000000000001c0 x26: 0000000000000001
[  165.142816] x25: ffffff800a20f000 x24: ffffff8009856018
[  165.148140] x23: ffffff8009531a48 x22: 0000000000000001
[  165.153391] x21: 00000000000001de x20: ffffff800a05b760
[  165.158477] x19: ffffff800a05b760 x18: 0000000000000010
[  165.164502] x17: 0000007fb1cdad40 x16: ffffff8008274b68
[  165.170191] x15: ffffffffffffffff x14: ffffff808a18e5b7
[  165.175876] x13: ffffff800a18e5c5 x12: 0000000000000000
[  165.181651] x11: 0000000005f5e0ff x10: 0000000000000403
[  165.187090] x9 : 00000000ffffffd0 x8 : ffffff80083d6cf0
[  165.192866] x7 : ffffff8009ef4468 x6 : 0000000000000000
[  165.198379] x5 : 0000000000000000 x4 : ffffffc1ffd03be8
[  165.203962] x3 : ffffffc1ffd03be8 x2 : 0000000000000007
[  165.209052] x1 : ffffff8009eb13c0 x0 : 0000000000010001
[  165.214639]
[  165.215790] Process swapper/0 (pid: 0, stack limit = 0xffffff8009ea0000)
[  165.222430] Call trace:
[  165.224540] [<ffffff8008cb3818>] tegra_cbb_error_isr+0x1a0/0x1a8
[  165.230399] [<ffffff8008121940>] __handle_irq_event_percpu+0x68/0x288
[  165.236520] [<ffffff8008121b88>] handle_irq_event_percpu+0x28/0x60
[  165.242383] [<ffffff8008121c10>] handle_irq_event+0x50/0x80
[  165.247722] [<ffffff8008125aa4>] handle_fasteoi_irq+0xd4/0x1c0
[  165.253064] [<ffffff80081208f4>] generic_handle_irq+0x34/0x50
[  165.258483] [<ffffff8008120fe0>] __handle_domain_irq+0x68/0xc0
[  165.263831] [<ffffff8008080d44>] gic_handle_irq+0x5c/0xb0
[  165.269157] [<ffffff8008082c28>] el1_irq+0xe8/0x194
[  165.273627] [<ffffff8008ba0d60>] cpuidle_enter_state+0xb8/0x380
[  165.279396] [<ffffff8008ba109c>] cpuidle_enter+0x34/0x48
[  165.284820] [<ffffff800811139c>] call_cpuidle+0x44/0x70
[  165.289895] [<ffffff8008111718>] cpu_startup_entry+0x1b0/0x200
[  165.295677] [<ffffff8008f6411c>] rest_init+0x84/0x90
[  165.300578] [<ffffff8009630b68>] start_kernel+0x374/0x38c
[  165.306000] [<ffffff8009630204>] __primary_switched+0x80/0x94
[  165.311609] ---[ end trace b2c0885f12ed7baf ]---
[  165.328905] Kernel panic - not syncing: Fatal exception in interrupt

This log is record with the Xavier NX’s default dts.
Xavier_NX_spi0_devmem_20220602_1955.log (65.6 KB)

Best Regards,
MOMO Chen

Dear Sir,

Update again. About the clock section.
I think we got few news that the SPI controller seems couldn’t generate higher frequency clock. It will be not neat above 5MHz, or no clock as we meet before.(Default value is 50MHz of dts that is no signal so far).

Example :
500KHz


5MHz

18MHz

In this situation, the tpm driver(the part of tpm_tis_core) always read 0x00 or 0xff while probe.

Example :
nVIDIA Xavier NX; the access is 0x0

[ 69.825015] [lanner_tpm][wait_startup:44]Self Test Begin, Expect : access & TPM_ACCESS_VALID(0x80) = true
[ 74.987734] [lanner_tpm][tpm_tis_spi_read_bytes:146]tpm_tis_spi_transfer addr=0x0,len=1
[ 74.987743] [lanner_tpm][tpm_tis_spi_transfer:68]
[ 74.988304] [lanner_tpm][wait_startup:51]tpm_tis_read8 rc=0,addr=TPM_ACCESS(1)=0x1000,access=0x0,jiffies=4294910848,stop=4294909749
[ 80.132327] [lanner_tpm][wait_startup:67]Time out jiffies is more than stop, return -1
[ 80.132338] [lanner_tpm][tpm_tis_core_init:741]wait_startup rc=-19

x86 Platform; the access is 0x81

[ 3749.199592] [lanner_tpm][wait_startup:44]Self Test Begin, Expect : access & TPM_ACCESS_VALID(0x80) = true
[ 3754.287622] [lanner_tpm][wait_startup:51]tpm_tis_read8 rc=0,addr=TPM_ACCESS(1)=0x1000,access=0x81,jiffies=4295829248,stop=4295828166
[ 3759.416446] [lanner_tpm][wait_startup:61]access & TPM_ACCESS_VALID = true
[ 3759.416447] [lanner_tpm][tpm_tis_core_init:718]wait_startup end

According our BIOS colleague shared, it will be 17MHz ~ 48MHz(default) in this x86 product at least. I will arrange to check the actually clock signal status in x86 platform.
Would you mind to help consult/check the clock, it couldn’t generate higher clock that expected or not?

p.s. we’re still couldn’t access spi controller’s register so far.

Best Regards,
MOMO Chen

Dear Sir,

Apologize for these mess.

  1. The clock could generate with higher freqeucy.
    Our logic analyzer’s sample rate is too low that couldn’t fetch the higher clock at all.
    We’ve use the oscilloscope to fetch it.
  2. We’ve also validated the TPM SLB9670 with Xaiver NX and the a x86 platform for compare.
    Our Hardware Engineer has create a post again, we might focus on this post first.
    TPM problem on SLB9670

Best Regards,
MOMO Chen