TPM problem on SLB9670

Hi Sir,

We have some problem on TPM, so we want check with you how we can do.
Our TPM on NX can’t initial.
Wish you can point out our mistake.

We use NX module, and TPM is SLB9670, schematic as below,

We measure waveform in initial, you can see photo as below

You can see MI and MO default is Low.
Our OS is Ubuntu.

And we use the same TPM(SLB9670) on other Linux Platform(X86, Ubuntu),
You can see MI and MO default is High.

So we have some question want to check in phenomenon:
Q1. Is our schematic need PU resistor?
PDG have no detail desciption in SPI pins.
Q2. It seems that MI and MO behavier is different on those platform,
we not sure which one is correct?
If x86 platform is correct? How can I adjust register?
Q3. X86 platfom CLK is longer than NX platform 8bit.
I not sure is it correct on NX platform. Or we have something worng?

Pin Matrix setting as below, is it correct?

If you need more detail setting, please let us know, we will provide it as soon as possible.
This problem bother us several weeks, hope we have some progress


Please refer to below topics to see if can help:
How to enable and test TPM2.0 module in Xavier? - Jetson & Embedded Systems / Jetson AGX Xavier - NVIDIA Developer Forums
How to enable TPM2.0 module in Xavier? - Jetson & Embedded Systems / Jetson AGX Xavier - NVIDIA Developer Forums

Dear kayccc,

As Allison’s mention about the Q3, we don’t understand “Why the NX’s clock is less than x86’s”

*For this photo, the up one is x86 platform and down one is Xavier NX.

So the Xavier NX only could get the read value/result 0x00 the show error code “-19” in the driver. (-19 indicate No such device)
But the x86 could get the read value/result 0x81

Xavier NX side

[   69.825015] [lanner_tpm][wait_startup:44]Self Test Begin, Expect : access & TPM_ACCESS_VALID(0x80) = true
[   74.987734] [lanner_tpm][tpm_tis_spi_read_bytes:146]tpm_tis_spi_transfer addr=0x0,len=1
[   74.987743] [lanner_tpm][tpm_tis_spi_transfer:68]
[   74.988304] [lanner_tpm][wait_startup:51]tpm_tis_read8 rc=0,addr=TPM_ACCESS(1)=0x1000,access=0x0,jiffies=4294910848,stop=4294909749
[   80.132327] [lanner_tpm][wait_startup:67]Time out jiffies is more than stop, return -1
[   80.132338] [lanner_tpm][tpm_tis_core_init:741]wait_startup rc=-19

x86 Platform side

[ 3749.199592] [lanner_tpm][wait_startup:44]Self Test Begin, Expect : access & TPM_ACCESS_VALID(0x80) = true
[ 3754.287622] [lanner_tpm][wait_startup:51]tpm_tis_read8 rc=0,addr=TPM_ACCESS(1)=0x1000,access=0x81,jiffies=4295829248,stop=4295828166
[ 3759.416446] [lanner_tpm][wait_startup:61]access & TPM_ACCESS_VALID = true
[ 3759.416447] [lanner_tpm][tpm_tis_core_init:718]wait_startup end

About those link you shared, I’ve add those parameter then tried to tune them.
But those parameter seems not effect the Q3 at all.

controller-data {
				nvidia,cs-setup-clk-count = <0x1e>;
				nvidia,cs-hold-clk-count = <0x1e>;				
				nvidia,rx-clk-tap-delay = <0x1f>;
				nvidia,tx-clk-tap-delay = <0x0>;
				nvidia,cs-inactive-cycles = <0x6>;		

tegra194-p3668-common_20220624_1111.dtsi (13.1 KB)
The left one argument is the cs-gpios, I think it should setting the cs to gpio in pinmux first,
then add the cs-gpios to the dts. Is that correct?

Is there any other argument might effect the Q3?
Would you mind to give us more suggestion for that.

Best Regards,

2022/06/24 Add; About the red section of pinmux table.
Should we need to adjust them that if we want use it as a GPIO with cs-gpios.

hello momo_chen,

the pinmux spreadsheets already define this pin as gpio.
you should also modify device tree as… gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(Z, 6) 0>;
then, you should be able control this pin through the code.

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