How to enable TPM2.0 module in Xavier?

Hi Sir:
I want to enable TPM2.0 driver in SPI1 in Xavier, following is the description in DTS file:

	spi@3210000 {
		status = "okay";
/*				
		spi@0 {
			compatible = "spidev";
			reg = <0x0>;
			spi-max-frequency = <33000000>;
			nvidia,enable-hw-based-cs;
			nvidia,rx-clk-tap-delay = <0x11>;
		};
*/
		slb9670: slb9670@0{
			compatible = "tcg,tpm_tis-spi";
			reg = <0x0>; /* CE0 */
			#address-cells = <1>;
			#size-cells = <0>;
			spi-max-frequency = <5000000>;
			nvidia,enable-hw-based-cs;
			status = "okay";
		};				
	};

The hardware circuit is :
圖片

But it seems doesn’t work. I also change the same setting on spi@c260000 and it can’t work too. Is there any suggestion? Thanks for help!!

hello robinchen,

had you co-work with your hardware engineer to probe the signaling for verification.

Hi Jerry:
Thanks. I will check with our hardware engineer. By the way, the dts description with spi interface for tpm2.0 module is correct or not? Do you have any reference code?

Hi Jerry:

I also reference SPI1 not work on Xavier , change the .cfg pinmux settings. And modify the dts as below:

	spi@c260000 {
		status = "okay";
		nvidia,clock-always-on;	
		slb9670: slb9670@0{
			compatible = "tcg,tpm_tis-spi";
			status = "okay";
			reg = <0x0>; /* CE0 */
			#address-cells = <1>;
			#size-cells = <0>;
			spi-max-frequency = <5000000>;
			nvidia,enable-hw-based-cs;
		};		
	};

Add “nvidia,clock-always-on;” description in dts file. The system got /dev/spidev0.0, but the tpm module can’t work too. Do you have any suggestion about this? Thanks!

hello robinchen,

it looks Xavier did not had internal TPM supports.

Hi Jerry:

After doing some modification, I got the message with “dmesg | grep spi”

user@user-desktop:~/spi-tools$ dmesg | grep spi
[    0.984506] iommu: Adding device 3210000.spi to group 12
[    0.985027] iommu: Adding device c260000.spi to group 13
[    2.225579] spi-tegra114 3210000.spi: Prod settings list not initialized
[    2.226316] spi-tegra114 3210000.spi: prod settings failed with error -22
[    2.226751] spi-tegra114 3210000.spi: registered master spi0
[    2.226943] spi spi0.0: setup 8 bpw, ~cpol, ~cpha, 5000000Hz
[    2.226951] spi spi0.0: child node 'controller-data' not found
[    2.226999] spi spi0.0: setup mode 0, 8 bits/w, 5000000 Hz max --> 0
[    2.227211] spi-tegra114 3210000.spi: registered child spi0.0
[    2.227236] spi spi0.1: setup 8 bpw, ~cpol, ~cpha, 33000000Hz
[    2.227243] spi spi0.1: child node 'controller-data' not found
[    2.227258] spi spi0.1: setup mode 0, 8 bits/w, 33000000 Hz max --> 0
[    2.227447] spi-tegra114 3210000.spi: registered child spi0.1
[    2.227561] spi-tegra114 c260000.spi: Prod settings list not initialized
[    2.228252] spi-tegra114 c260000.spi: prod settings failed with error -22
[    2.228703] spi-tegra114 c260000.spi: registered master spi1
[    6.719483] spi-tegra114 3210000.spi: Setting clk_src pll_p
[    6.719895] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.719996] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.736841] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.736940] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.752432] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.752738] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.768432] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.768700] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.784982] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.785710] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.800456] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.800551] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.816481] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.817353] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.833176] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.833458] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.848389] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.850867] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.864418] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.864500] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.880399] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.880484] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.896409] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.896501] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.916400] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.916756] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.932636] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.933081] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.948467] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.948557] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.964502] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.964608] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.980485] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.980588] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    6.996457] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.996556] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.012414] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.012503] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.028423] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.028493] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.044833] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.044920] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.060442] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.060537] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.076424] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.076512] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.092423] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.092531] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.108414] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.108506] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.124449] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.124547] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.140408] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.140497] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.156393] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.156478] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.172443] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.172549] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.188789] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.188903] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.204884] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.204992] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.220701] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.220822] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.240461] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.240569] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.256420] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.256511] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.272779] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.272885] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.292761] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.292844] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.308421] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.308519] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.324438] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.324554] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.340440] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.340511] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.356426] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.356550] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.372420] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.372487] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.388414] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.388477] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.404425] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.404523] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.420425] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.420493] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.436407] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.436490] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.456413] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.456483] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.472401] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.472469] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01027
[    7.472543] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.472605] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e00827
[    7.472655] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.472716] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007
[    7.472766] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    7.472815] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e008

It seems the system try to enable the device, but something went wrong. Is there any suggestion about this? Thanks.

Please add the prod-settings like below. And move the “nvidia,enable-hw-based-cs” into the controller-data{}

       spi@c260000 {
                status = "okay";
                spi-max-frequency = <65000000>;
                prod-settings {
                        #prod-cells = <3>;
                        prod {
                            prod = <0x04 0x0000003f 0x0f>;
                        };
                };

                spi@0 {
                        compatible = "spidev";
                        reg = <0>;
                        nvidia,raw_data;
                        spi-max-frequency = <51000000>;
                        controller-data {
                                nvidia,variable-length-transfer;
                        };
                };

Hi ShaneCCC:

After modify the dts file, the dmesg are:

user@user-desktop:~$ dmesg | grep spi
[    0.964181] iommu: Adding device 3210000.spi to group 12
[    0.964804] iommu: Adding device c260000.spi to group 13
[    2.040351] spi-tegra114 3210000.spi: prod settings failed with error -19
[    2.040867] spi-tegra114 3210000.spi: registered master spi0
[    2.041182] spi spi0.0: setup 8 bpw, ~cpol, ~cpha, 500000Hz
[    2.041325] spi spi0.0: setup mode 0, 8 bits/w, 500000 Hz max --> 0
[    2.041556] spi-tegra114 3210000.spi: registered child spi0.0
[    2.041591] spi spi0.1: setup 8 bpw, ~cpol, ~cpha, 500000Hz
[    2.041602] spi spi0.1: child node 'controller-data' not found
[    2.041621] spi spi0.1: setup mode 0, 8 bits/w, 500000 Hz max --> 0
[    2.041794] spi-tegra114 3210000.spi: registered child spi0.1
[    2.041920] spi-tegra114 c260000.spi: Prod settings list not initialized
[    2.042832] spi-tegra114 c260000.spi: prod settings failed with error -22
[    2.043171] spi-tegra114 c260000.spi: registered master spi1
[    6.661431] spi-tegra114 3210000.spi: Setting clk_src clk_m
[    6.661845] spi-tegra114 3210000.spi: prod settings failed with error -19
[    6.661852] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01827
[    6.662056] spi-tegra114 3210000.spi: The def 0x47d08000 and written 0x43e01007

And the dts file that I modify as below:

	spi@3210000 {
		status = "okay";
		prod-settings {
			#prod-cells = <3>;
			prod {
				prod = <0x04 0x0000003f 0x0f>;
			};
		};

		spidev: tpm@0{
			compatible = "tcg,tpm_tis-spi";
			status = "okay";
			reg = <0x0>; 
			#address-cells = <1>;
			#size-cells = <1>;
			spi-max-frequency = <500000>;			
			controller-data {
				nvidia,variable-length-transfer;
				nvidia,enable-hw-based-cs;
			};
		};

Are there any missing? Any suggestions? Thanks.
By the way, the TPM module connect to spi@3210000, the prod settings is correct or not?

Hi ShaneCCC:

After we check with out TPM module vendor, the CS need active low in whole tx/rx process. Please Check the waveform below:

For DTS settings, how can I keep CS pin low in whole rx/tx process?

spidev: tpm@0{
			compatible = "tcg,tpm_tis-spi";
			status = "okay";
			reg = <0x0>; 
			#address-cells = <1>;
			#size-cells = <1>;
			spi-max-frequency = <500000>;			
			controller-data {
				nvidia,enable-hw-based-cs;
				nvidia,cs-setup-clk-count = <0x1e>;
				nvidia,cs-hold-clk-count = <0x1e>;				
				nvidia,rx-clk-tap-delay = <0x1f>;
				nvidia,tx-clk-tap-delay = <0x0>;
				nvidia,cs-inactive-cycles = <0x6>;		
			};
		};

Thanks for help.

Could you have a reference to …/kernel/kernel-4.9/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
to add below properties to try.

nvidia,cs-setup-clk-count : CS setup timing parameter.
nvidia,cs-hold-clk-count : CS hold timing parameter.

Hi robinchen,

Have you clarified the cause and resolved the issue?
Any result can be shared?

Hi kayccc:
We have add “nvidia,cs-setup-clk-count” & “nvidia,cs-hold-clk-count”, and both values were set to “0x7f”, but the tpm module still can’t work. Are there any detail description about these two properties?

Hi Robinchen,

Is your TPM working with Xavier ?
If yes, can you share DTS entry ?

Thanks
Alks

CS is main issue during TPM bringup. Need to define as “cs-gpios”.

And then it will work.

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