The use case would be with an FPGA that can produce a maximum TX MIPI channel of 1 clk + 4 data lanes using the D-PHY architecture, meaning I can only go up to 10Gbps for one channel. The FPGA does not support 1x8 MIPI architecture, but can support numerous 4 lane channels for sending MIPI data. For scalability and dealing with possible overhead issues (I’m going to be using 20Gbps of raw data for current use case, but want to be able to support up to the Xavier NX’s maximum of 30Gbps) I wanted to have three of the 4 lane channels, each acting as a separate link that I could stitch together on the other end.
The idea I had was single high speed camera input that could be split and reordered on the GPU side to maximize flexibility, i.e:
20-30Gbps high frame rate stream → sub stream assignment based on frame number → send via designated mipi channel → Jetson side concatenate frames in kernel driver after frame is received by ISP → make DMA memory address accessible to CUDA and or user apps, swap DMA address buffer as needed based on read ptr of application.
Would the above possibly work? Are there examples of attempts using this type of restructuring of image stream to increase bandwidth limitations of MIPI CSI-2? Is there a frame count register available in the ISP for frame counting and reordering on GPU kernel side?
I found this link regarding another user wanting 1x12 MIPI, but I am strictly constrained to 3 x 4 lane mipi.
Link: CSI Interface -- one 12 lanes configuration possible or not???