CSI Interface -- one 12 lanes configuration possible or not???

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

Hi All,

As per Jetson Tx2 TRM, in nvcsi controller, it supports the three 4 lanes configurations.
Whether nvcsi controller can support one 12 lanes configurations or not?
Please provide your input on this.

In one device tree configurations, in vi controller device node, nvcsi controller device node, specific device node, bus width is configured as “bus-width = 8”, i.e. it supports one 8 lanes configurations.
How nvcsi controller supports this configuration?

port@0 {
reg = <0>;
status = “okay”;
csi_in0: endpoint@0 {
status = “okay”;
csi-port = <0>; bus-width = <8>;
remote-endpoint = <&out0>;
};
};

If configure the “bus-width = 12” in media controller link in device tree node, then will it support the one 12 lanes configuration.

Please confirm this.

-Thanks.

2

Hi, all CSI configurations are listed in table 48 of OEM DG, there is no direct way of supporting more than that.

3

hello BalajiNP,

there’s HDMI to CSI bridge driver that use 8-lanes, you could check kernel driver tc358840.c for more details.
about your 12-lane configuration. may i know what’s your hardware device, and what’s the use-case?
thanks

4

Hi JerryChang,

Thanks for the inputs.

We need to give CSI output to Jetson Tx2 board. This is for Ultra HDMI to CSI conversion.

In TC358840 chip datasheet, it is given as:

  • Dual links CSI-2 (CSI0 and CSI1), each link supports 4 data lanes @ 1 Gbps/data lane
  • CSI0 carries the left half data of HDMI Rx video stream and CSI1 carries the right one at the
    default configuration.
  • Left or right data can be assigned/programmed to either CSI-2 Tx link

I am looking into how this works in CSI controller. What kind of configuration we have to do for this?
Default configuration is enough or need to configure in different way to perform this??
Please provide your inputs on this.

Whether we need to look for MIPI specification or nvcsi controller details to get the idea on this.
Need the help on this.

-Thanks.

5

hello BalajiNP,

for the 8-lane use-case, there’s configuration in the device tree to specify 8-lanes and VI kernel driver will choose gang mode to handle the streaming.

still curious about more details for your use-case.
for example, is this single chip HDMI-CSI bridge? may i know what’s the resolution?
thanks

6

Hello JerryChang,

Whether Nvcsi controller supports 8 lanes? Please provide the specific details about this.

Consider the use case as SDI to CSI bridge? Checking the feasibility for this.
The resolution is: 3840x2160@30Hz Or 3840x2160@60Hz.

Please share your ideas.

-Thanks.

7

Hello JerryChang,

Use case is:

We are building FPGA based video bridge (HDMI & SDI to MIPI CSI-2) which should support upto 4Kp60 and max speed of upto 12G.

-Thanks.

8

Hi All,

Any Ideas on this topic.

-Thanks.

9

hello BalajiNP,

each CSI lane of TX2 can support up-to 2.5Gbps,
consider your use-case, 3840x2160@60Hz should be 3840x2160x16(2byte)x60= 7.9Gbps
may i know what’s the “units” of your 12G streaming?
thanks

10

Hi JerryChang,

Thanks for the reply.

The input from FPGA to each CSI lane of Tx2 is 1Gbps. This limitation is due to FPGA device. Since this FPGA device comes under our product’s cost. Other FPGA devices (high data bandwidth supports ~1.5Gbps) are not in our product’s cost.

Use case is:

  1. 12-G SDI requires - 12Gbps
  2. 3840x2160p@60fps with 24 bits per pixel - 3840x2160x60x24=11.89 Gbps

We are looking for this FPGA device. Thanks for the inputs.

-Thanks.

11

Hi All,
Any ideas on this?

12

@BalajiNP:

Why do you want to convert the 10bit 422 video to 8bit 444?
That just increases the data rate from 20bpp to 24bpp.

We have worked with SDI using PCIe. The 4x3G capture device is right on the edge of what Tegra PCIe can do and FPGA’s in reasonable costs. 12G is just a question of adding a gearbox IC. If you are interested, contact me.

For CSI you have to use either a faster I/O to fit into 8lane CSI, or to use software postprocessing to merge the three CSI inputs into one. AFAIK the nvidia drivers can not share CSI buffers (we would like that as well, for synchronized camera capture).

There is no 12 lane decoding mode (Parker TRM is very clear on this).

13

Nvidia,

Any input from Nvidia Engineers??

-Thanks.

14

hello BalajiNP,

please check comment #9

each CSI lane of TX2 can support up-to 2.5Gbps,

you should be able to configure 8-lane (8*2.5Gbps= 20Gbps) for your use-case.

[i]Use case is:
1. 12-G SDI requires - 12Gbps
2. 3840x2160p@60fps with 24 bits per pixel - 3840x2160x60x24=11.89 Gbps[/i]
15

Hi JerryChang,

please check comment #10 and help us.

-Thanks

16

@NVIDIA Engineers

FPGA outputs 12-G SDI in the form of 12 lanes (three CSI ports) of MIPI CSI outputs each capable of 1Gbps line rate.

Can Nvcsi Controller be configured in 1x8 and 1x4 lanes and can be applied to merge in software application or software post-processing to merge the three CSI inputs into one?

If FPGA interfaces to NVIDIA TX2 in PCIe the data bandwidth issue is resolved. However, there is only memory coming up with PCIe unlike VI for CSI-2.

Look forward to hear from you.

Regards,
Aasim