Vi controller -- Channel match to Streams -- Doubts

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

Hello All,

In Vi controller, in register, VI_CH_MATCH_0,
STREAM values are programmed.

From nvcsi, 3 Bricks are there, so configures to 3 streams, each 4 lanes.
Can I configure all 3 streams (each 4 lanes) from nvcsi to single Vi channel? Each stream bandwidth is 4Gbps and total bandwidth is 12Gbps to 14 Gbps.
Whether Vi controller pipeline has fifo memory or other configurations for this scenario.

As per TRM Vi sections and register details, Vi can handle this configuration.
I want to confirm this configuration. Datatype is YUV422-8 or RGB888.

-Thanks.

2

hello BalajiNP,

Can I configure all 3 streams (each 4 lanes) from nvcsi to single Vi channel?
that means total 12-lanes into VI channel. however, NVCSI do NOT support 12-lane configuration.
thanks

3

Hello JerryChang,

Thanks for the reply.

I knew that Nvcsi does not support 12-lanes configurations and 8-lanes configurations too.

For example, Toshiba chip TC358840 based board, it provides 8-lanes configurations to
Nvcsi (by split the video as left and right and left video goes to first CSI brick and right goes to 2nd CSI brick.) into two 4 lanes and then in Vi driver, using ganged mode, they are merged.

Here, Vi controller receives the two CSI bricks data into one single channel.

Again please go through this query and provide your inputs.

-Thanks.

4

hello BalajiNP,

you may refer to VI kernel driver for more details,

<top>/kernel_src/kernel/kernel-4.4/drivers/media/platform/tegra/camera/vi/channel.c

please also refer to the device tree settings as below.

<top>/kernel_src/hardware/nvidia/platform/t18x/quill/kernel-dts/quill-modules/tegra186-camera-imx274.dtsi

                tc358840@1f {
                                    ...
                                        tc358840_out0: endpoint {
                                                csi-port = <2>;
                                                <b>bus-width = <8>;</b>
                                                remote-endpoint = <&tc358840_csi_in0>;
5

Hello JerryChang,

I have gone through these files. Regarding software, I do not have any doubts.

The doubt is in: Vi controller’s channel capacity or capability, i.e. Vi controller’s internal FIFO depth, internal clock, external clock, operating clock, voltage level, configuration mode and etc.

From Nvcsi, 3 streams (Each 4 lanes) from 3 bricks are configured into Vi controller single channel. Whether single channel has capacity to receive from all 3 streams?
Here, capacity means Vi controller’s or channel’s internal FIFO depth, internal clock, external clock, interface clock, operating clock, voltage level, configuration mode, internal architeture and etc.

Please provide your inputs.

-Thanks.

6

Hello All,

Any inputs on this query?

-Thanks.

7

hello BalajiNP,

you’re asking about the VI capability, please check the maximum throughput from below documentation.
thanks

[Tegra TRM]-> [Video Input (VI)]-> [Performance]