If the depths don’t match, then it’s unclear how the extra address bits into the LUT are wired. Are the extra bits at the MS end, LS end, or what ? Are they wired to 0, 1 or something else, such as some of the other address bits ? Where in the XRandR API is this defined, so that this can be handled automatically by the software, for hardware that makes different choices of the above ?
[ i.e. the API would be much cleaner if the hardware didn’t expose this mismatch. ]
Without that being defined, it’s not possible to know what to put in the LUT, hence the assert in the ArgyllCMS code.