Add a YUV camera with CPHY mode on Jetson AGX Orin(t234)

[Kun_Wang]

Now I bringup a 5MP YUV camera use CPHY mode, and I refer the tegra234-camera-e3331-a00.dtsi to modify my dtsi files, such as phy_mode = “CPHY”, num_lanes = “3”.
Q1: THe deserializer has output the CPHY mipi data normal, but the VI module report timeout error, what is the reason? Is the pix_clk_hz need to config?

[Kevin_Wang2025]

					mode0 {/*mode OX05B1S_MODE_2592X1944_CROP_30FPS*/
						mclk_khz = "24000";
						num_lanes = "3";
						phy_mode = "CPHY";
						tegra_sinterface = "serial_e";
						discontinuous_clk = "no";
						dpcm_enable = "false";
						cil_settletime = "30";

						active_w = "2592";
						active_h = "1944";
						mode_type = "yuv";
						pixel_phase = "uyvy";
						csi_pixel_bit_depth = "16";
						readout_orientation = "0";
						line_length = "2592";
						inherent_gain = "1";
						mclk_multiplier = "31.25";
						pix_clk_hz = "750000000";

						gain_factor = "16";
						framerate_factor = "1000000";
						exposure_factor = "1000000";
						min_gain_val = "16"; /* 1.0 */
						max_gain_val = "256"; /* 16.0 */
						step_gain_val = "1"; /* 0.125 */
						default_gain = "16";
						min_hdr_ratio = "1";
						max_hdr_ratio = "1";
						min_framerate = "1500000"; /* 1.5 */
						max_framerate = "30000000"; /* 30 */
						step_framerate = "1";
						default_framerate= "30000000";
						min_exp_time = "34"; /* us */
						max_exp_time = "550385"; /* us */
						step_exp_time = "1";
						default_exp_time = "33334";/* us */
						embedded_metadata_height = "0";
					};
					ports {
						#address-cells = <1>;
						#size-cells = <0>;
						port@0 {
							reg = <0>;
							fzcam_out0: endpoint {
								//vc-id = <0>;
								port-index = <4>;
								bus-width = <3>;
								remote-endpoint = <&fzcam_csi_in0>;
							};
						};
					};

And the deserializer CPHY data is 5244 Mbps/lane, how to calculate pix_clk_hz? Please help me to review the params config if right? Thank you!

[JerryChang]

hello Kevin_Wang2025,

you don’t need to configure pix_clk_hz if that’s using a SerDes chip.
please note that, serdes_pix_clk_hz should be greater than or equal to pix_clk_hz, it depends-on your actual use-case.

[Kevin_Wang2025]

Hi Jerry,
The num_lanes parameter’s value what I should config? 3 or 2 ?

[sgursal]

For Deserializer connections example, please refer to the deserializer device vendor design collateral and NVIDIA Jetson AGX Xavier Series and Jetson AGX Orin Series Camera Module Hardware Design Guide Log in | NVIDIA Developer

[Kun_Wang]

@Kevin_Wang2025

The num_lanes

Hi sgurasal,
The num_lanes in dtsi file, what’s value to config when in CPHY mode?

[sgursal]

Please refer to the AGX Orin Design Guide. CPHY uses Trios. 1/2/3/4-Trios are supported. Use only the default mapping as shown in the design guide. Others not supported in SW.

[JerryChang]

hello Kun_Wang,

@Kun_Wang

The num_lanes in dtsi file, what’s value to config when in CPHY mode?

just setting the device tree as same as your hardware connections.