There are the following problems while checking the HDMI output value while changing the EDID.
HDMI Pixel Clock adjustment problem!
The current issue is as follows.
a. Display Pixel Clock desired by EDID: 25.02MHz
b. HDMI Pixel Clock output from TX2 (by external measurement): 25.82MHz
There is a problem that the pixel clock must be set to 25 MHz as much as possible due to the characteristics of the LCD to be controlled.
Is there a way to improve or control this part?
How to check the actual output HDMI Pixel Clock
When TK1 advantage was confirmed by outputting the actual output that most closely calculated the EDID of the Pixel Clock debug messages to the kernel.
“nominal-pclk:%d parent:%lu div:%lu.%lu pclk:%lu %d~%d\n”,
mode->pclk, rate, (div + 2) / 2, ((div + 2) % 2) * 5, pclk,
mode->pclk / 100 * 99, mode->pclk / 100 * 109);
However, TX2 does not know how to check the value of Pixel Clock actually calculated and output.
In addition, HDMI’s Pixel Clock, which was not implemented in TK1 at HD resolution, has been created in TX1 / TX2.
Is it possible to make the HDMI Pixel Clock more precise in TX2?
I want to know if there is a way to check or control this part.
And I want to know if Xavier has been improved in this direction.