Wrong timing values of HDMI port

Hi all,
We made a customized board. There is a hdmi-to-edp converter chip on our board.
The converter chip shows the timing values of video recieved in debug messgaes.
We find the timing values of hdmi port are wrong according to these debug messages.
This problem sometimes will casue no video output on monitors.

Values of relative registers are following.

DC_DISP_DISP_TIMING_OPTIONS             405     00000001
DC_DISP_REF_TO_SYNC                     406     00010001
DC_DISP_SYNC_WIDTH                      407     0005002c
DC_DISP_BACK_PORCH                      408     001e0072
DC_DISP_DISP_ACTIVE                     409     04380f00
DC_DISP_FRONT_PORCH                     40a     00040066

It shows H_SYNC_WIDTH is 44 and H_DISP_ACTIVE is 3840.
But in debug messages of chip, it shows H_SYNC_WIDTH is 50 and H_DISP_ACTIVE is 3837.

Is there any register or setting I can check?

tegradc.1regs.txt (13.9 KB)
chip_message.txt (345 Bytes)

Hi FrankPCP,

Could you paste the EDID of that HDMI and the edid read in tegra?

The edid read in tegra would be in /sys/kernel/debug/tegradc.X/edid

Hi WayneWWW,
tegra_edid.txt is the edid dumped from /sys/kernel/debug/edid1 and hdmi_edid.txt is edid from monitor.

The horizontal timing values are not stable. I did’t find vertical timing value changed.
I dumped the register of tegradc.1 when I got the different H timing values. Basically they are same.
H_Sync_W_40.txt is register dumped when h sync width is 40. H_Sync_W_50.txt is in 50.


H_Sync_W_40.txt (13.3 KB)
H_Sync_W_50.txt (13.3 KB)
hdmi_edid.txt (406 Bytes)
tegra_edid.txt (536 Bytes)

The EDIDs match and are valid (they’re formatted differently in terms of bytes listed per line, but they are the same bytes). You might add this to the “/etc/X11/xorg.conf” Section “Device”:

Option   "ModeDebug"

If you boot with that option you will find increased detailed information in “/var/log/Xorg.0.conf” after a reboot. Perhaps it may say something about the mode you are looking at.

Hi Frank,

What is the result of /sys/kernel/debug/tegradc.0/mode ?

Hi WayneWWW,

The tegradc.0 is used for edp and tegradc.1 is for hdmi on our board.


pclk: 275330000
h_ref_to_sync: 0
v_ref_to_sync: 3
h_sync_width: 44
v_sync_width: 5
h_back_porch: 114
v_back_porch: 30
h_active: 3840
v_active: 1080
h_front_porch: 102
v_front_porch: 4
stereo_mode: 0


pclk: 275330000
h_ref_to_sync: 1
v_ref_to_sync: 1
h_sync_width: 44
v_sync_width: 5
h_back_porch: 114
v_back_porch: 30
h_active: 3840
v_active: 1080
h_front_porch: 102
v_front_porch: 4
stereo_mode: 0

Hi FrankPCP,

Could you elaborate more about how this HDMI-eDP converter works? It looks like tegra side receive a correct EDID, however, your chip does not output correctly.

Hi WayneWWW,

The HDMI-eDP converter receives hdmi signals from tk1 and coverts hdmi to edp.
There is a uart interface on the converter chip.
We can connect this uart interface via UART to USB module and receive debug messages from the chip.
The chip will print the timing values of the hdmi signal once it get hdmi input.
We check these debug messages and find the H timing values are unstable.
This problem sometimes will cause no video output on monitors or sometimes output blur images.

I believe this converter is out of tegra scope. In previous data you provided, I see tk1 receive the correct EDID from eDP (it should be eDP but not HDMI in #2, sorry for this) and set the mode correctly.

It may be the issue of that chip driver. Could you check it first? Is tk1 output signal unstable as well?

Hi FrankPCP,

Have you clarified and resolved the problem?
Any result can be shared?


Hi kayccc,
No, not yet.
We are still finding ways to check the stability of signal of TK1 hdmi output.

Hi All,
I got a hdmi-to-dp reference board and tested it with jetson TK1.
I found when I set the resoultion to 3840x2160, the timing values of hdmi port would be unstable as well as our customized board.
So I think there might be some timing problem in hdmi port when resolution is high.

cat_tegradc1_mode.txt (265 Bytes)
cat_tegradc1_regs.txt (13.8 KB)
hdmi-to-edp-messages.txt (977 Bytes)

edid.txt (1.04 KB)

Hi FrankPCP,

How about directly connect a 4K@30 HDMI monitor to tk1 board? Is the signal also unstable?

Hi WayneWWW,
I test two 4k monitors with Tk1 board. One is LG 24UD58, the other is ASUS PB279Q.
Please refer to link below for specifications.


No issues occur in testing with LG 24UD58. Images output is OK and no blur images.
But when I test Tk1 with AUSU PB279Q, no images output on monitor.
Because I don’t have HDMI analyzer, I can’t measure the timing values of hdmi port.
I am not sure if this is caused by wrong timing value.
Do you have HDMI analyzer or can you see what’s wrong with hdmi port from attached logs?
Asus_cat_edid1.txt (1 KB)
Asus_cat_regs.txt (13.9 KB)
Asus_cat_mode.txt (269 Bytes)
Xorg.log.txt (19.2 KB)
xrandr_verbose.txt (8.26 KB)
Asus_dmesg.txt (58.1 KB)

I doubt tk1 chooses a unsupported mode when Asus monitor is used. There is similar bug on tx1/tx2 on rel-28.1.

Just a tip…if a signal goes to a monitor, and the monitor does not like the signal, it will typically make a brief complaint about “signal out of range”. Unplug the monitor and plug it back in…note carefully if there is a brief complaint from the monitor, or if it simply does not find a signal. There is a difference between the two.

Also, I mentioned “ModeDebug” earlier. Booting with the monitor which does not work, and then looking at the “/var/log/Xorg.0.log” from serial console or ssh would tell you exactly what the NVIDIA driver thinks of the mode being attempted with that monitor. It could have nothing to do with timing and the test does not require any special equipment. It is so much easier to simply ask the driver what it thinks than to try to figure it out with other methods.

Hi WayneWWW,
I used another hdmi cable for testing and tk1 can show images on ASUS monitor correctly.

I found another thing. On our customize board, the pixel clock value required in edid is 275.27MHz. But I see the pixel clock set in hdmi port is 273000000 hz.

[   62.330301] tegradc tegradc.1: nominal-pclk:275330000 parent:546000000 div:2.0 pclk:273000000 272576700~300109700

Could this be the reason why H timing values are unstable?

Hi FrankPCP,

This value is calculated by dc driver and maybe rounded because of parent clock. Could you trace “tegra_dc_pclk_round_rate” and see why this value changes?

Hi WayneWWW,
I trace the drivers/video/tegra/dc/hdmi.c. There is a function “tegra12x_hdmi_determine_parent” and it adjusts parent clock as a multiples of 12000000Hz.

parentClk = 12000000*m (m=1,1.5,2,2.5....)

That’s why the pclk can’t be the exact value required in edid.

My question is:
Is this a restriction of hardware or is there any way I can set the pclk as the exact value required in edid?


Hi FrankPCP,

This is how parent clk is determined but not the place where pclk is determined. I think the problem should be why pclk=273000000?