Hi All,
I notice that the pixel clock of HDMI can only be a multiple of 12000000 HZ.
In kernel/drivers/video/tegra/dc/hdmi.c
static unsigned long tegra12x_hdmi_determine_parent(
const struct tegra_dc *dc, struct clk *parent_clk, int pclk)
{
/* T124 hdmi pclk:
* parentClk = pclk * m (m=1,1.5,2,2.5,...,128.5)
* (refclk * n) = pclk * m (n=1,1.5,2,2.5,...,128.5)
* (no half resolutions for m due to uneven out duty cycle)
* (refclk * N / 2) = pclk * m (N=2,3,4,...,257)
* m = (refclk / 2 * N) / pclk (m=1,2,3,...,128)
* looking for N to make m whole number
*/
int n, m;
int b, fr, f;
/* following parameters should come from parent clock */
const int ref = 12000000; /* reference clock to parent */
const int pmax = 600000000; /* max freq of parent clock */
b = 0;
fr = 1000;
for (n = 4; (ref / 2 * n) <= pmax; n++) {
if ((ref / 2 * n) < pclk) /* too low */
continue;
m = DIV_ROUND_UP((ref / 2 * n), (pclk / 1000));
f = m % 1000; /* fractional parts */
f = (0 == f) ? f : (1000 - f); /* round-up */
if (0 == f) { /* exact match */
if ((ref / 2 * b) < 100000000) {
/* parent clock runs at a minumum of 100MHz */
continue;
}
b = n;
fr = f;
break;
} else if (f < fr) {
b = n;
fr = f;
}
}
return (unsigned long)(ref / 2 * b);
}
I would like to know if this is the hardware limitation?
Can we set a specific pixel clock something like 275330000HZ?