AGX Orin UPHY2 Lane(RX2/TX2, RX3/TX3) Configuration as PCIE connecting to SATA chip(88SE9170)

[wangzhiwei1]

We designed a custom board for AGX Orin 64GB(p3701-0005), using UPHY2 Lane(RX2/TX2, RX3/TX3) connect to 88SE9170 as a PCIe to SATA bridge. we have done:

1. Downloaded pinmux table and change the usage of UPHY2 Lane(RX2/TX2, RX3/TX3)
   
   
2. Generarted pinmux.dtsi and gpio.dtsi, renamed these two files: tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi, tegra234-mb1-bct-gpio-p3701-0000-a04dtsi, replaced gpio file in /…/Linux_for_Tegra/bootloader and pinmux file in /…/Linux_for_Tegra/bootloader/t186ref/BCT/.
3. Enabled PCIe with tegra234-p3737-pcie.dtsi in /…/JetPack_5.1.2_Linux_JETSON_AGX_ORIN_TARGETS/Linux_for_Tegra/sources/hardware/nvidia/platform/t23x/concord/kernel-dts/cvb/ as below:
   pcie@141e0000 {
   status = “okay”;
   num-lanes = <8>;
   phys = <&p2u_gbe_0>, <&p2u_gbe_1>, <&p2u_gbe_2>,
   <&p2u_gbe_3>, <&p2u_gbe_4>, <&p2u_gbe_5>,
   <&p2u_gbe_6>, <&p2u_gbe_7>;
   phy-names = “p2u-0”, “p2u-1”, “p2u-2”, “p2u-3”,
   “p2u-4”, “p2u-5”, “p2u-6”, “p2u-7”;
   };
   also tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi in /…/Linux_for_Tegra/bootloader/t186ref/BCT/ :
   pex_l7_clkreq_n_pag0 {
   nvidia,pins = “pex_l7_clkreq_n_pag0”;
   nvidia,function = “pe7”;
   nvidia,pull = <TEGRA_PIN_PULL_NONE>;
   nvidia,tristate = <TEGRA_PIN_DISABLE>;
   nvidia,enable-input = <TEGRA_PIN_ENABLE>;
   nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
   nvidia,lpdr = <TEGRA_PIN_DISABLE>;
   };
4. Changed ODMDATA in p3701.conf.common located on /…/Linux_for_Tegra/ ODMDATA=“gbe-uphy-config-22,hsstp-lane-map-3,nvhs-uphy-config-0,hsio-uphy-config-0,gbe0-enable-10g”;
5. Maked .dtb and copied tegra234-p3701-0005-p3737-0000.dtb and tegra234-p3701-0000-p3737-0000.dtb from /…/kernel_output/arch/arm64/boot/dts/nvidia/ to /…/Linux_for_Tegra/kernel/dtb/
6. Burning successfully with sudo ./flash.sh -r jetson-agx-orin-devkit intenal, but can not find any PCI bridge and SATA controller.
   I donot know what’s wrong with above steps and what shall I do.
   Thanks a lot!
   dtsi.zip (6.5 KB)

[WayneWWW]

Attach your dmesg.

[wangzhiwei1]

Thank you for your reply! I deleted /boot/dtb/kernel-tegra234-p3701-0005-p3737-0000.dtb, and remove FDT in /boot/extlinux/extlinux.conf, it can successfully detect SATA controller by RX2/TX2, but RX3/TX3 still failure. and when I reboot, sometimes it can not detect any SATA controller, sometimes is OK to detect SATA controller by RX2/TX2. I don’t know why, anyway I will attach dmesg.
Another question for pinmux table, when I only confige RX2/TX2, or confige both RX2/TX2 and RX3/TX3, the pinmux.dtsi generated is all same, is it the right case?

[WayneWWW]

1. it can successfully detect SATA controller by RX2/TX2, but RX3/TX3 still failure.

請問你是用什麼依據得出這個結論的…?

2. Another question for pinmux table, when I only confige RX2/TX2, or confige both RX2/TX2 and RX3/TX3, the pinmux.dtsi generated is all same, is it the right case?

本來pcie lane本身就不用改pinmux… 沒人請你作這一部份的更改… 只有clkreq那幾根需要改pinmux…

[wangzhiwei1]

1. 我们使用了2片88SE9170，分别接到RX2/TX2和RX3/TX3上，在连接到使用RX2/TX2的88SE9170上接了硬盘，通过lspci和lsblk查到了SATA Controller和硬盘。
   
   
2. 对于pinmux.dtsi, 有两处修改，rst和clkreq：
   pex_l7_rst_n_pag1 {
   nvidia,pins = “pex_l7_rst_n_pag1”;
   nvidia,function = “pe7”;
   nvidia,pull = <TEGRA_PIN_PULL_NONE>;
   nvidia,tristate = <TEGRA_PIN_DISABLE>;
   nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
   nvidia,lpdr = <TEGRA_PIN_DISABLE>;
   };

pex_l7_clkreq_n_pag0 {
nvidia,pins = “pex_l7_clkreq_n_pag0”;
nvidia,function = “pe7”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

另外giop.dtsi，也删除了TEGRA234_MAIN_GPIO(AG, 1)
TEGRA234_MAIN_GPIO(AG, 0)
TEGRA234_MAIN_GPIO(AG, 2)
TEGRA234_MAIN_GPIO(AG, 3)
如果不需要修改pinmux， 请问除了clkreq，还有什么需要修改？
感谢！！

[WayneWWW]

Hi,
…請問一下你到底在做什麼… 什麼叫分別接到RX2, RX3上面???
你是希望能一次跑兩個88SE9170?? 聽起來你對這整個硬體能支援的功能沒有搞清楚…

[wangzhiwei1]

您好！

是的，我是想一次跑两个88SE9170， 分别使用UPHY2 lane0 和lane1， 请问可以这样使用吗？

Best Regards,

Bruce Wang

[WayneWWW]

不行…你右邊那個PCIE C7就是一個PCIe controller (Root port)… 一次只能控制一個pcie device…

[wangzhiwei1]

那使用PCIE C7连接SATA芯片，就只能要么使用UPHY2, Lane0(RX2/TX2)，要么使用UPHY2, Lane1(RX3/TX3)？

[WayneWWW]

你只能用UPHY2, Lane0(RX2/TX2)

[wangzhiwei1]

好的，感谢！