I got confused from the Block Diagram provided by Nvidia ,
- How Raw Video Data is transfered from CSI to H/W encoder?
I assume this the path, but i can’t find the exact path
CSI --> VI --> CPU --> GPU --> H/W
Kindly can anyone help me out to find how the data follows.
I have went through the sample codes(tegra_multimedia_api) & the docs nvl4t_docs.
For tegra_multimedia_api\samples\10_camera_recording, it is
CSI camera input -> camera ISP -> DMA buffers -> Video encode
Please check out this “Getting Started with the JetPack Camera API” PDF: http://on-demand.gputechconf.com/gtc/2016/webinar/getting-started-jetpack-camera-api.pdf
The presentation was for TX1, but I think it most likely applies to TX2 as well.
Thanks Danel for quick reply .
It really helped me solve most of my confusion.
And I have few more quires
for the tegra_multimedia_api\samples\12_camera_v4l2_cuda, IT has same path ? .
for audio path will be I2s --> device memory --> Host Memory --> APC . Is this correct ?
Thanks jkjung13 , The document you provided has good info , which I can use for development of product using TX2 libargus .