Can not reduce the SPI frequency below 3.3 MHz

I can not reduce the SPI frequency below 3.3MHz.

I changed
static __initdata struct tegra_clk_init_table ardbeg_clk_init_table

{ “sbc1”, “pll_p”, 3300000, false},

in file board-ardbeg.c

As soon as I reduce 3300000 to 1000000 I see a bump in the frequency to 30MHz.

I saw same issue where someone was complaining about the SPI frequency:

But there is no workaround posted. Please help ASAP.

Hi there
Could you confirm to enable spidev by kernel config and DT to verify the spidev_test can set the frequency as you want.

./spidev_test -D /dev/spidev0.1 -s1000000 -g8 -b8 -p0 -n1 -zzz -t

changing the parent clk source to clk_m will reduce the frequency.

pll_p has a limit on max frequency
clk_m has lower max freq than pll_p
also need to tweak dts files and spi driver to reduce and take the frequency that we want.