Carrier Board doubts

Hi there,

I’m taking inspiration from the open designs of the carrier board to make my own.
And next doubts come to my mind, hope someone can clarify them:

  • USB3.0: I want to put a two entry stacked USB3.0 in the board. I have seen the next table in OEM guide:

I would like to use the Use Case #2 or #3, so I can connect two different USB3.0 ports to the connector. The Note sections says that might not be support in the Software release… That’s a definitive decision or could we have two USB3.0 supported interfaces?
If so, which Jetson TX1 pins should I use, PEX1 or SATA?

  • HDMI: I have checked Carrier Board design and the OEM guide mentioned above and see that the HDMI has a filter activated with an Enable for data and clock lines.

Is there any problem if I leave it always enabled? Meaning that I do not put a FET and connect it to GND.

If that is not a good idea, in the carrier board you use a I2C expander to generate this enable signal. Could I use an Jetson TX1 pin straight to generate EN signal?

  • Discharge circuit: Does TX1 module needs discharge circuitry for the different voltages?

Regards

Imuguruza

It looks like you’re referring to the 499ohm pulldowns and 600ohm beads to GND through the FET. This is actually not filtering. The Tegra X1 pads used for HDMI are not actually TMDS pads (TMDS is what HDMI uses), but are DP pads. The AC caps and pulldowns are there to convert the signals to TMDS levels. The enable is there because by HDMI spec, the pulldowns cannot be active because this will affect the termination voltage which must be AVcc +/- 10mV. The pulldowns will cause this termination (equivalent to 50ohm to AVcc rail) to be below the spec. I believe this may only a spec. compliance issue, and shouldn’t cause functional issues, but I don’t know the actual reason for this spec. It may be that additional power would be consumed – not sure.

On your own carrier board, assuming you are removing the I2C expander, you can use another GPIO from the JTX1 module to generate the signal.

Although the multi-USB3 is configured out of the box in software, in theory you should be able to get it working by editing the DTS/DTB device tree and referencing the TX1 TRM and pinmux. From the pinmux, you can use either PEX1 or PEX3, and switching one of these could enable the 2nd USB superspeed. See the selected area of this screenshot for PEX3:

Hi dusty_nv,

First of all thanks for the support!

A couple of doubts:

  • HDMI: I’m concerned about how to calculate Max trace length for HDMI data and clk. OEM design guide says:
    Trace loss charac.: <0.8 dB/in @ 3GHz
    <0.4 dB/in@1.5Ghz Max length is derived based on this characteristics

Not sure about how can I know if my design meets this requirement…

  • USB 3.0

Although the multi-USB3 is configured out of the box in software, in theory you should be able to get it working by editing the DTS/DTB device tree and referencing the TX1 TRM and pinmux. From the pinmux, you can use either PEX1 or PEX3, and switching one of these could enable the 2nd USB superspeed. See the selected area of this screenshot for PEX3:

OK, i’ll use those pins for a secondary USB3.0. There is any chance of doing it also USB2.0 compatible?? The only possibility that comes to mind is to use USB0-D +/- signals again… (already used in the other USB port)

For this second USB3.0 port, which pin can I use USB_EN?? USB2_EN_OC# (A19) is not exposed. So, how can I turn this port on??

Confirm please that those PEX0 pins need also 0.1uF caps (in serie), as suggested in page 11 and 13 of the OEM Product Design Guide (Under 3.0 Jetson TX1 Pin description)

  • Discharge circuit: Does TX1 module needs discharge circuitry for the different voltages?

Thanks in advance,

IMuguruza

There are additional characteristics listed in the table on page 37 of the OEM DG.
The trace lengths correspond to the different L sections in the HDMI clk/data topology:

The biggest section of consequence, from L4 to the HDMI connector, should be <12.7mm.

The PEX0_TX diff pair should be terminated in series with 0.1uF caps near main connector, and PEX0_RX should be terminated in series with 0.1uF caps near peripheral if directly connected.

You shouldn’t have to worry about the TX1 rails local to the module. However the carrier does require discharge circuitry for the 5V0, 3V3, and 1V8 supplies on the carrier. After detecting the power transition, the circuitry grounds the supplies pictured in figure 5 on page 17 of the OEM DG:

Thanks again for the response, still have some unresolved doubts about USB3.0 enable

Is it possible to make 2nd USB port 2.0 version compatible?
The only possibility that comes to mind is to use USB0-D +/- signals again… (already used in the other USB port)

For this second USB3.0 port, which pin can I use USB_EN?? USB2_EN_OC# (A19) is not exposed. So, how can I turn this port on??

Regards,

Imuguruza

Any news @Dusty?? I would like to know how to make both ports USB3.0 andd 2.0 backwards compatible…

Regards

There are 3 sets of USB2 ports available, the signals are USB[2:0]_D– and USB[2:0]_D+

Here are the pin numbers for the USB2 ports:

B39 USB0_D+ (Micro USB Data+)
B40 USB0_D- (Micro USB Data-)
A38 USB1_D+ (USB 2.0, Port 1 Data+)
A39 USB1_D- (USB 2.0, Port 1 Data-)
B42 USB2_D+ (USB 2.0, Port 2 Data+)
B43 USB2_D- (USB 2.0, Port 2 Data-)

Here are the pin numbers for the second USB3:

D42 USB_SS1_TX+
D43 USB_SS1_TX-
G42 USB_SS1_RX+
G43 USB_SS1_RX-

In the diagram below, if you wire up the top USB2 port to be like the bottom USB2/3, to include the USB_SS1 superspeed signals listed above (those USB_SS1 pins aren’t pictured in the diagram), you could in theory use USB0_EN_OC#, providing both ports USB3.0 and 2.0 backwards compatible:

If you require more, separate ports, I think VBUS sensing is not required for bus-powered devices.
Initially, for your first hardware revision, we recommend little deviation from the reference schematic.

Thanks!

Imuguruza