Discrepancy in CPHY Pin Mapping Documentation - Jetson Thor Design Guide

Robotics & Edge Computing Jetson & Embedded Systems Jetson Thor
1

Hello Nvidia,

I have identified a discrepancy in the CPHY pin connections documented in the Jetson Thor Series Modules Design Guide (DG12084001_v1.2.pdf).

Documented Pin Connections:

  1. Figure 10-2. Camera CSI C-PHY Connections:
  • CSI_0_CLK_N connects to CPHY_01_A
  • CSI_0_D1_P connects to CPHY_01_B
  • CSI_0_D1_N connects to CPHY_01_C

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  1. Table 10-1. Jetson Thor CSI Pin Description:
  • CSI0_CLK_N connects to CPHY Lane 1: C
  • CSI0_D1_P connects to CPHY Lane 1: A
  • CSI0_D1_N connects to CPHY Lane 1: B

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My Questions:

  1. Which mapping (Figure 10-2 or Table 10-1) is the correct one for the physical pin connections?
  2. Our custom carrier board was designed based on the mapping in Figure 10-2. During debugging, we are encountering the following errors in the kernel trace log:
kworker/11:1-145 [011] ..... 1003.879920: rtcpu_nvcsi_intr: tstamp:1030300663207 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x00000080
kworker/11:1-145 [011] ..... 1003.879921: rtcpu_nvcsi_intr: tstamp:1030301722578 class:GLOBAL type:PHY_INTR0 phy:0 cil:0 st:0 vc:0 status:0x20000080

The status codes 0x00000080 and 0x20000080 often point to issues like incorrect lane mapping or signal integrity problems potentially related to the pin assignment. Is it possible to remap these CPHY lane connections through software configuration? If so, how can we adjust the configuration to align with the hardware mapping we used (based on Figure 10-2)?

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