Displayport output on TX2

Hello,
I have a custom carrier board that I have designed to output displayport on DP1 instead of HDMI. It was designed according to the TX2 TRM 7.2.1 Figure 24 on page 42.

I am unable at this time to get a signal output out of the displayport connector, unplugging and plugging in the does not register an event on the log. The kernel log shows the following on boot with the connector disconnected

[    5.373691] hpd: hpd_switch 0
[    5.373696] hpd: switching from state 0 (Reset) to state 1 (Check Plug)
[    5.373699] tegradc 15220000.nvdisplay: blank - powerdown
[    5.385171] hpd: state 1 (Check Plug), hpd 0, pending_hpd_evt 0
[    5.385179] hpd: switching from state 1 (Check Plug) to state 3 (Disabled)
[    5.401485] hpd: hpd_switch 0
[    5.404452] hpd: switching from state 0 (Reset) to state 1 (Check Plug)
[    5.413142] hpd: state 1 (Check Plug), hpd 0, pending_hpd_evt 0
[    5.419087] hpd: switching from state 1 (Check Plug) to state 3 (Disabled)

The pin is enabled via device tree with the following snippet added to the pinmux_default node

dp_aux_ch0_hpd_pp0 {
	nvidia,pins = "dp_aux_ch0_hpd_pp0";
	nvidia,function = "dp";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

dp_aux_ch1_hpd_pp1 {
	nvidia,pins = "dp_aux_ch1_hpd_pp1";
	nvidia,function = "dp";
	nvidia,pull = <TEGRA_PIN_PULL_NONE>;
	nvidia,tristate = <TEGRA_PIN_ENABLE>;
	nvidia,enable-input = <TEGRA_PIN_ENABLE>;
	nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
	nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

I have also enabled sor and sor1 as displayport nodes with both their aux lines enabled in an attempt to see something useful.

Any help would be greatly appreciated.

kernel.log (97.9 KB)
tegra186-quill-p3310-1000-c03-00-base.dts.txt (373 KB)

Did you change the pinmux setting (dp_aux_ch1_hpd_pp1) inside the pinmux spreadsheet as well?

Hi WayneWWW,
Yes I did change the pinmux in the spreadsheet to DP_AUX_CH1_HPD, pin direction=INPUT, wake pin=yes,3.3v tolerance=no, LPDR enable=no.

Then exported a dtsi file. I only added the pin dt node to my device tree in tegra186-quill-p3310-1000-c03-00-base.dts under the relevant parent node

pinmux@2430000 {
    common {
        ......
        dp_aux_ch1_hpd_pp1 {
        .......
        }
    }
}

Between then and now I also decided to run the following commands after reading the L4T docs.

python pinmux-dts2cfg.py \
    --pinmux \
    addr_info.txt gpio_addr_info.txt por_val.txt \
    mandatory_pinmux.txt \
    tegra18x-jetson-tx2-config-template-pinmux.dtsi \
    tegra18x-jetson-tx2-config-template-gpio-default.dtsi \
    1.0 \
> tegra186-quill-p3310-1000-a00-pinmux-gpio.cfg
python pinmux-dts2cfg.py \
    --pad pad_info.txt \
    tegra18x-jetson-tx2-config-template-padvoltage-default.dtsi \
    1.0 \
    > tegra186-mb1-bct-pad-quill-char-e3301-1080-a00.cfg

copied the outputs to /bootloader/t186ref/BCT/ as described in the section “TX2 Configuring Pinmux GPIO and PAD” of the nvl4t_docs

I then run the ./flash.sh jetson-tx2 mmcblk0p1
The result is a new message but still no DP output. The message is the same for dp plugged in at boot and hotplugged after boot.

[   10.590420] tegradc 15210000.nvdisplay: dp: HPD is not detected
[   10.590424] tegradc 15210000.nvdisplay: dp: Failed to read DPCD data. CMD 0x1, Status 0x0
[   10.605232] tegradc 15210000.nvdisplay: dp: HPD is not detected
[   10.605234] tegradc 15210000.nvdisplay: dp: Failed to read DPCD data. CMD 0x1, Status 0x0

coldboot.log.txt (87 KB)

Please check the runtime device tree is correct through the /proc/device-tree node.

Currently these are the outputs

/proc/device-tree/host1x/dpaux@15040000/status
okay

/proc/device-tree/host1x/dpaux@155c0000/status
okay

/proc/device-tree/host1x/sor1/status
okay

/proc/device-tree/host1x/sor1/dp-display/status
okay

/proc/device-tree/host1x/sor/status
okay

/proc/device-tree/host1x/sor/dp-display/status
okay

/proc/device-tree/host1x/nvdisplay@15200000/status
disabled

/proc/device-tree/host1x/nvdisplay@15210000/status
okay

/proc/device-tree/host1x/nvdisplay@15220000/status
disabled

Is there any other nodes I should be checking. I also noticed in the pinmux HDMI_DP1 has the signals
DP0_TX2+/-
DP0_TX1+/-

Thinking it was backwards I tried enabling nvdisplay@15220000 so both DP0 and DP1 are on but still no display output.

For clarification, our DP connector is on the same DP lines as the HDMI connector on the devkit, DP1 in the device tree on sor1.
I have also tried changing polarity on the HPD pin in sor and sor1 from GPIO_ACTIVE_LOW to GPIO_ACTIVE_HIGH

nvidia,hpd-gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(P, 1) GPIO_ACTIVE_HIGH>;

but still nothing…

Per checked your dts and it looks correct. In our dts, you can see we just have a small change as “tegra186-quill-p3310-1000-a00-00-dsi-dp.dts” to enable DP on dp1.

Also, the hpd-gpio should be still GPIO_ACTIVE_LOW.

If these dt change still don’t get the dp link training to start, please refer to our OEM design guide for reviewing your hardware design.