Hello NVIDIA,
I have a device upstream that sends CSI-2 packets in MIPI CSI-2 High Speed mode only. It never switches to MIPI CSI-2 Low-Power mode (except at initialization when it goes from LP to HS mode). After it sends the first CSI-2 packet, it stays in high speed mode.
Would this be an acceptable interface to the NVCSI block or will I run into problems?
The NVCSI CIL seems to react to and control for LP/HS transitions. What happens if there are no transitions?
I see that there is a Watchdog timer in the NVCSI CIL to guard against no EoT detection. Is there a way to disable this? Is it the same as PPFSM Timeout controls for the 6 NVCSI Streams?
Would the asynchronous FIFO between the NVCSI CIL and the NVCSI CORE eventually overflow if the camera keeps the interface in CSI-2 high speed mode (HS-mode)?
Does keeping the camera interface in CSI-2 high speed mode (HS-mode) affect the skew calibration feature of the NVCSI CIL?
LP state is required between CSI-2 packets. Does the device really sent out only ONE very long packet? Per the CSI-2 spec, the largest packet size is 65536 bytes.
Currently NVCSI design doesn’t support LRTE feature, so after the packet complete, all the following data are dropped if not return to LP11. The watchdog timer can be disabled and FIFO will not overflow.
The device sends out short and long packets, but it stays in HS state. After the device sends a Frame Start short synchronization packet, it stays in HS state and then sends a Line Start short synchronization packet then sends a Long Packet. The time between these packets can vary. Would this be an issue? Is returning to the LP state between CSI-2 packets a requirement by the NVCSI block?
