i am developing a custom bridge board for AGX Thor using Holoscan Sensor Bridge architecture. My goal is to transfer multiple sensor data to GPU memory via Zero-copy, using only the integrated MGBE port on Thor (no external ConnectX NIC)
- Platform: NVIDIA AGX Thor (Integrated MGBE)
- Sensors: Lidar (Pointcloud), Radar ADC raw data, and IMU.
- Interfaces: MIPI CSI-2 and Custom LVDS (to be interfaced via FPGA).
- Target Bandwidth: Total ~10GbE.
I am aware that Thor’s MGBE doesn’t support ROCE and instead uses the IEEE1722 CoE hardware engine for CPU offloading. i have the following technical questions to determine out FPGA IP design.
- Support for Generic Payloads for CoE
- Can the IEEE 1722b engine handle non-video data types(like Lidar and Radar ADC)for zero-copy? if we encapsulate these as generic data, will the hardware still offload them to GPU memory?
- For cam with internal ISPs, can we use SIPL FuSa functions to receive the data in Zero-copy form?
- CSI-2 Emulation
- If the IEEE 1722b engine is strictly optimized for video, is it a viable workaround to encapsulate Lidar data into “Pseudo-CSI-2” frames (using specific Data Types) at the FPGA level to trigger the Zero-copy path?
- SPI Data Handling
- For low-bandwidth data like IMU, Radar, is it possible to mix Zero-copy(via 1722)and standard linux UDP sockets on the same MGBE port simultaneously?
- SIPL compatibility
- Since our sensors are not standard cameras, can we use the SIPL Capture operator or custom UDDF driver to interface with the 1722b engine for these non-video sensors?
Any guidance on the packet headers or encapsulation requirements needed to satisfy the Thor MGBE’s hardware offload engine would be extremely helpful for our Bridge Board development.
Thank you