from #2 configuration (4x1, 1x1 configuration) to #3 Configuration (1x1, 1x1, 1x1 configuration)

rbthakre · August 24, 2018, 6:59am

I have changed from #2 configuration to #3 configuration by changing in

tegra186-quill-p3310-1000-c03-00-base.dts
Change ODMdata=0x6090000 in p2771-0000.conf.common for #3 configuration

all requried changes done by my side and it is showing 1x1, 1x1, 1x1 configuration in dmesg but also showing ‘disable power rail’ due to which devices(sensoray 812, exar xr17v35x) not showing connection on pcie by lspci command. Please tell me what should i do to work on #3 configuration.

I am sharing a Output of “dmesg | grep pci”

GPIO line 459 (pcie-lane2-mux) hogged as output/low
iommu: Adding device 10003000.pcie-controller to group 50
tegra-pcie 10003000.pcie-controller: 1x1, 1x1, 1x1 configuration
tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
tegra-pcie 10003000.pcie-controller: probing port 0, using 1 lanes
tegra-pcie 10003000.pcie-controller: probing port 1, using 1 lanes
tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
tegra-pcie 10003000.pcie-controller: link 0 down, retrying
tegra-pcie 10003000.pcie-controller: link 0 down, retrying
tegra-pcie 10003000.pcie-controller: link 0 down, retrying
tegra-pcie 10003000.pcie-controller: link 0 down, ignoring
tegra-pcie 10003000.pcie-controller: link 1 down, retrying
tegra-pcie 10003000.pcie-controller: link 1 down, retrying
tegra-pcie 10003000.pcie-controller: link 1 down, retrying
tegra-pcie 10003000.pcie-controller: link 1 down, ignoring
tegra-pcie 10003000.pcie-controller: link 2 down, retrying
tegra-pcie 10003000.pcie-controller: link 2 down, retrying
tegra-pcie 10003000.pcie-controller: link 2 down, retrying
tegra-pcie 10003000.pcie-controller: link 2 down, ignoring
tegra-pcie 10003000.pcie-controller: PCIE: no end points detected
tegra-pcie 10003000.pcie-controller: PCIE: Disable power rails

what should i do resolve issue of power rail?

Thanks in Advance

WayneWWW · August 28, 2018, 2:59am

rbthakre,

Is you device being detected on devkit with 4 lane configuration?

rbthakre · August 28, 2018, 5:31am

Hi ,
Thanks for a reply.

yes device being detected on devkit with 4 lane configuration. but not on 1 lane configuration.

WayneWWW · September 6, 2018, 6:55am

Have you checked this thread?
https://devtalk.nvidia.com/default/topic/1038894/jetson-tx2/tx2i-configuration-3/2

Please make sure “pcie0_lane2_mux” is set.

rbthakre · September 7, 2018, 6:03am

Hi,

Thanks for reply. I have checked that thread already but no progress issues still same.
i am working on a Nvidia jetosn TX2 development kit . I thought #3 configuration must be easy. but i dont know what i am missing.

“pcie0_lane2_mux” is set.

rbthakre · September 7, 2018, 6:05am

Hi,

i have followed all steps given in this thread for #3 configuration.

https://elinux.org/Jetson/TX2_USB

WayneWWW · September 7, 2018, 6:36am

Please follow up this thread and see if anything is missing.

https://devtalk.nvidia.com/default/topic/1038894/j

rbthakre · September 10, 2018, 9:17am

Hi,

Memory dump is ok

sudo devmem2 0x02520284 b => 1 (PCIe - LANE0 PEX1)
sudo devmem2 0x02530284 b => 0 (XUSB - LANE1 PEX_RFU)
sudo devmem2 0x02540284 b => 0 (XUSB - LANE2 USB_SS1)
sudo devmem2 0x02550284 b => 1 (PCIe - LANE3 PEX2)
sudo devmem2 0x02560284 b => 1 (PCIe - LANE4 PEX0)
sudo devmem2 0x02570284 b => 2 (SATA - LANE5 USB_SS0)

$ ls -l /proc/device-tree/chosen/plugin-manager/odm-data

total 0
-r–r–r-- 1 root root 4 Sep 2 06:57 android-build
-r–r–r-- 1 root root 4 Sep 2 06:57 disable-pmic-wdt
-r–r–r-- 1 root root 4 Sep 2 06:57 disable-sdmmc-hwcq
-r–r–r-- 1 root root 4 Sep 2 06:57 disable-tegra-wdt
-r–r–r-- 1 root root 4 Sep 2 06:57 enable-debug-console
-r–r–r-- 1 root root 4 Sep 2 06:57 enable-denver-wdt
-r–r–r-- 1 root root 4 Sep 2 06:57 enable-pcie-on-uphy-lane0
-r–r–r-- 1 root root 4 Sep 2 06:57 enable-pcie-on-uphy-lane4
-r–r–r-- 1 root root 4 Sep 2 06:57 enable-sata-on-uphy-lane5
-r–r–r-- 1 root root 4 Sep 2 06:57 enable-xusb-on-uphy-lane1
-r–r–r-- 1 root root 4 Sep 2 06:57 enable-xusb-on-uphy-lane2
-r–r–r-- 1 root root 9 Sep 2 06:57 name
-r–r–r-- 1 root root 4 Sep 2 06:57 no-battery
-r–r–r-- 1 root root 4 Sep 2 06:57 normal-flashed

still same error is coming i am not missing anything.

rbthakre · September 10, 2018, 9:17am

My devkit is Nvidia Jetson TX2

WayneWWW · September 10, 2018, 9:24am

rbthakre,

Why did you mention devkit here? It should your own carrier board.
Devkit does not support config#3 at all.

rbthakre · September 10, 2018, 10:35am

There is no specific reason behind mention devkit here. I thought for better clearance i should mention. Apologies if i did something wrong.

Okay that’s why the output i want was not coming because Devkit was not supported config #3.

Thanks for a help

rbthakre · September 10, 2018, 11:12am

hi,

If i design my own carrier board based on Jetson -TX2 som module, what are the necessary changes to be done for config #3 ?
Will i able to use PCIE X1?

WayneWWW · September 11, 2018, 1:56am

rbthakre,

Our devkit only supports config #1 and config #2 from the tx2 adaptation guide. As a result, there is already a PCIe x1 enabled if you use config#1 on devkit. However, that PCIe x1 on devkit is used by the M.2 key slot, so it might not be what you want.

If you want to design your own carrier board, please firstly follow our oem product design guide.(OEM DG)

After hardware design, please follow the method in adaptation guide or follow the thread I posted in previous comment.

I think all possible mistakes had been listed in this user’s topic.

rbthakre · September 11, 2018, 6:17am

As per the OEM guide in config#3 we are able to achieve 3-PCIe x1 (i.e. PCIe#0_0, PCIe#1_0 and PCIe#2_0) which is our requirement.

In devkit(P2597-C02) we have PCIE x4 slot(J2) in which PCIe#0_0 is available. So using a mini pcie-card adapter can’t we able to test PCIe x1 as PCIE x4 slot is always compatible with PCIE x1.

WayneWWW · September 11, 2018, 9:19am

rbthakre,

It should work if you use x1 to the x4 slot.

rbthakre · September 11, 2018, 11:05am

Ok

2nd Issue: I am using Exar xr17v35x on a PCIE for Serial Communication . I am using driver xr17v35x .
Steps i am following are

        1. $ lspci -vd 13a8:*

    01:00.0 Serial controller: Exar Corp. Device 0354 (rev 03) (prog-if 02 [16550])
Flags: fast devsel, IRQ 388
Memory at 50100000 (32-bit, non-prefetchable) 
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [78] Power Management version 3
Capabilities: [80] Express Endpoint, MSI 01
Capabilities: [100] Virtual Channel
Kernel driver in use: xrserial

      2. ls  /sys/bus/pci/drivers/serial/

      0000:01:00.0 bind new_id remove_id uevent unbind

      3. $ echo -n "0000:01:00.0" > /sys/bus/pci/drivers/serial/unbind

This is unbinding the generic serial driver from XR17V35x device

      4. insmod xr17v35x.ko

So port ttyXR0, ttyXR1, ttyXR2, ttyXR3 is creating in /dev/

But when i am doing a loopback test i am not getting output . It is showing “Read Error”. It is not Communicating serially.

I am doing this on #2 configuration.

Do i need to set some pin for serial communication??

rbthakre · September 12, 2018, 8:49am

x1 is working in the x4 slot in config#2.

But my concern is if we are configuring devkit in config#3 were we are able to achieve 3-PCIe x1 (i.e. PCIe#0_0, PCIe#1_0 and PCIe#2_0) and PCIe#0_0 is available in PCIE x4 slot(J2) so why we cant able to use it??