Get low EMMC performance on SDMMC3

We are trying to port Sandisk SDINADF4-64G-H on SDMMC3 with our carrier board. The kernel we are using is L4T R24.2. We can bring it up but we found the write speed is not quiet good. For now, we try to configure the host controller to support HS200 with 4 bit :

sdhci@700b0400 { /* SDMMC3 for EMMC */
		tap-delay = <1>;
		trim-delay = <3>;
		nvidia,ddr-tap-delay = <0>;
		mmc-ocr-mask = <0>;
		max-clk-limit = <200000000>;
		ddr-clk-limit = <48000000>;
		uhs-mask = <0x5c>;  //Only leave HS200 available
		bus-width = <4>;
		calib-3v3-offsets = <0x007D>;
		calib-1v8-offsets = <0x7B7B>;
		compad-vref-3v3 = <0x7>;
		compad-vref-1v8 = <0x7>;
		pll_source = "pll_p";
		status = "disabled";

but the clock rate is around 163 Mhz:

cat /sys/kernel/debug/clock/sdmmc3/rate


and the write speed is around 65MB/s with tested by :
dd bs=8M count=128 if=/dev/zero of=/home/myhome/test.txt conv=fdatasync

Is there any one have any idea why the clock rate is limited to 163 Mhz ?
I think the write speed should be increased if the clock rate can reach to 200 Mhz.

Is this tested on your own designed carrier board? If so, firstly you need to follow the layout guideline in OME Design Guide.

We’ve checked the design guide, the resistor of sdio_clk/sdio_cmd line are reverse. We’ve exchanged the resistor of CLK/CMD and test again, unfortunately, the eMMC clock frequency is still 163.2MHz.

The frequency is depend on the clock source and clock divider, the actual frequencies may be lower due to clock source/divider limiattions

Also, you could check the freqency with CMD as below (The SDMMC4(on board emmc) is on and clock is 199.68MHz during data access):
root@tegra-ubuntu:/sys/kernel/debug/clock# cat clock_tree | grep mmc
sdmmc4.emc off 0 1065600000 (150000000) sdmmc3.emc off 0 1065600000 (1600000000)
sdmmc4 on 0 1.0 199680000 sdmmc_legacy off 0 34.0 12000000 *sdmmc4_ddr off 0 9.0 45333334 sdmmc2_ddr off 0 9.0 45333334 sdmmc2 off 0 2.0 204000000
sdmmc3_ddr off 0 9.0 45333334
*sdmmc1_ddr off 0 9.0 45333334
sdmmc3 off 0 9.0 45333334 sdmmc1 off 0 4.0 102000000
sdmmc4.sclk $ off 0 12218750 (115000000)


Did you try another PLL source as below:

pll_source = “pll_p”, “pll_c4_out2”;

Hi Trumany,

We just tried it and the clock rate can reach 199.68 MHz, and the write speed can reach ~76 MB/s. I think it do increase the performance, thanks for support.


Hi Trumany,

After doing the stress test, we found the write speed is not stable. The write speed goes from 30MB/s to 75MB/s.

Here is the command we are using for testing speed:

 dd bs=8M count=128 if=/dev/zero of=/home/myhome/test.txt conv=fdatasync

We also found a post about the EMMC slow sequential write problem :

The post said need to set CPU freq and EMC freq to max speed also enable all CPU online before doing the IO testing.
Could you please share us how to set CPU and EMC freq to max and enable all CPU online on tx1 ? thanks.


We’ve found a post about Maximizing TX1 Performance, we’ll try it first, thanks.


The vendor has give us an information that the buffer inside the EMMC might be full to cause the low write speed. They want us to set a EXT_CSD[163] register value as “2h” to enable the BKOPS, so the buffer will be empty in background.
I’ve checked the device tree and didn’t see any configuration for the EXT_CSD register, could you please share us how to configure the EXT_CSD register ?



Will the driver support the “Auto BKOPs” function ?

kernel/drivers/mmc/core/mmc.c has support the feature for eMMC as below.

            /* check whether the eMMC card supports BKOPS */
            if (ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1) {
                    card->ext_csd.bkops = 1;
                    card->ext_csd.bkops_en = ext_csd[EXT_CSD_BKOPS_EN];
                    card->ext_csd.raw_bkops_status =
                    if (!card->ext_csd.bkops_en)                                                                                                                                                                 
                            pr_info("%s: BKOPS_EN bit is not set\n",

Hi Vicky,

I just print out the value of “card->ext_csd.bkops_en”, and it’s “1h”. Is there any way can set it to “2h” ?


I’m not familiar with EXT_CSD[163] but I believe you can just check if mmc_start_bkops() is taking effect in kernel/drivers/mmc/core/core.c or not.

We’ve checked following code that related to BKOPs, and none of these are invoked during the read/write of EMMC.
Do you have any idea when will these condition be satisfied ?


if (brq->cmd.resp[0] & EXT_CSD_URGENT_BKOPS)

In “/drivers/mmc/card/queue.c”

if (mmc_card_need_bkops(mq->card))
          mmc_start_bkops(mq->card, true);

In “/drivers/mmc/core/core.c”

		 * Check BKOPS urgency for each R1 response
		if (host->card && mmc_card_mmc(host->card) &&
		    ((mmc_resp_type(host->areq->mrq->cmd) == MMC_RSP_R1) ||
		     (mmc_resp_type(host->areq->mrq->cmd) == MMC_RSP_R1B)) &&
		    (host->areq->mrq->cmd->resp[0] & R1_EXCEPTION_EVENT))
			mmc_start_bkops(host->card, true);

Which EMMC are you talking about? Does it support BKOPS?

We are using “SDINADF4-64G-H” and it needs BKOPs to clean up cache to resolve the performance drop issue.

I would like to attach a image to describe the BKOPs requirement in data sheet, but I don’t know how to do that ?

hello MKAO,

you’re able to attach the files by “EDIT” your own comment,
there’s a needle pin icon at the top right of the comment for you to upload the attachment.

Thanks Jerry, I can successfully attache the image.


I just found a document that briefly introduce the EMMC SLC cache and the driver support they expected (P22) :

We also see the software feature list of R24.1 has mentioned the BKOPS only available on SDMMC4, could you please also help confirm whether the BKOPS is available on SDMMC3 or not ? thanks.