How to configure SPI2 as a slave?

Hi ShaneCCC
Please answer me some questions
1: which address is SPI2 address, is 0xc260000?
2: set the SPI2 as slave mode - ( SPI2 = spi1, if SPI1 = spi0(the address is 3210000)) , the pinmux settings is what?
3: i will change the dt as below , is there any problems?

spi@c260000 {
		status = "okay";	//zp add
		spidev@0 {
			status = "okay";
	        compatible = "nvidia,tegra186-spi-slave";
	        spi@0 {
	            compatible = "spidev";
	            reg = <0>;
	            spi-max-frequency = <33000000>;
	            controller-data {
	                nvidia,enable-hw-based-cs;
	            };
	        };
		};
	};

Thanks so much for your answer and help.

                spi0 = "/spi@3210000";
                spi1 = "/spi@c260000";
                spi2 = "/spi@3230000";

  1. The pinmux configure are the same with master mode.
  2. No
1 Like

and the pinmux setting is set as below, if you say the master mode and the slave mode is same, so the below setting is useful, right?

pinmux.0x0c302048 = 0x00000400; # spi2_sck_pcc0: spi2, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0c302050 = 0x00000450; # spi2_miso_pcc1: spi2, tristate-enable, input-enable, io_high_voltage-disable, lpdr-disable
pinmux.0x0c302028 = 0x00000400; # spi2_mosi_pcc2: spi2, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0c302038 = 0x00000400; # spi2_cs0_pcc3: spi2, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable

Have program them as below.

pinmux.0x0243d040 = 0x00000450; # spi1_sck_pz3: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d020 = 0x00000450; # spi1_miso_pz4: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d058 = 0x00000450; # spi1_miso_pz4: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d010 = 0x00000448; # spi1_cs0_pz6: rsvd1, pull-up, tristate-disable, input-enable, lpdr-disable
pinmux.0x0243d010 = 0x00000448; # spi1_cs0_pz6: rsvd1, pull-up, tristate-disable, input-enable, lpdr-disable

What is the command to get the receive date from spi2?
I use the command as below to get the date, but it does not work correctly.

root@dev-desktop:~/lab# ./spidev_test -D /dev/spidev1.0 -p dummy-8B
spi mode: 0x0
bits per word: 8
max speed: 12500000 Hz (12500 KHz)
can't send spi message: Invalid argument
Aborted (core dumped)

Could you enable SPI1 as mast and connect the SPI1 to SPI2 as loopback to run the test.

Does the SPI1 and SPI2 have internal connect channel for loopback test?

No, you have connect them from external.

Hi ShaneCCC
my spidev_test app does not have the ‘-g’ ‘-n’ options.

root@dev-desktop:~/lab# ./spidev_test_fpga -D /dev/spidev1.0 -s 12500000 -N 0  -g30 -p4 -z
./spidev_test_fpga: invalid option -- 'g'
Usage: ./spidev_test_fpga [-DsbdlHOLC3vpNR24SI]

Get the binary from below.

Hi i use your executable file,and dmesg as below


root@dev-desktop:~/lab# ./spidev_test -D /dev/spidev0.0 -s 150000 -n100 -g30 -p4 -z &
[1] 10769
root@dev-desktop:~/lab# using device: /dev/spidev0.0
spi mode: 0
bits per word: 8 bytes per word: 1
max speed: 150000 Hz (150 KHz)
no. runs: 100
/dev/spidev0.0: TEST FAILED !!!!! (status:-1)

[1]+  Exit 1                  ./spidev_test -D /dev/spidev0.0 -s 150000 -n100 -g30 -p4 -z
root@dev-desktop:~/lab#
root@dev-desktop:~/lab#
root@dev-desktop:~/lab# ./spidev_test -D /dev/spidev1.0 -s 150000 -n100 -g30 -p4 -z
using device: /dev/spidev1.0
spi mode: 0
bits per word: 8 bytes per word: 1
max speed: 150000 Hz (150 KHz)
no. runs: 100
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1
transfer ioctl error: -1

spidev0.0 as spi master
spidev1.0 as spi slave, what command can let spidev1.0 used as slave mode to receive data

Make a script like below to run it.

sudo ./spidev_test -D /dev/spidev0.0 -s8000000 -g512 -b32 -H -p0 -n1 -r &
sleep 5
sudo ./spidev_test -D /dev/spidev1.0 -s8000000 -g512 -b32 -H -p0 -n1 -zzz -t

spidev0.0 still TEST error

root@dev-desktop:~/lab# ./spi.sh
/dev/spidev0.0: TEST FAILED !!!!! (status:-1)
Disabling receive
using device: /dev/spidev1.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 1
bits per word: 32 bytes per word: 4
max speed: 8000000 Hz (8000 KHz)
no. runs: 1
Using seed:0x61078f1a
loop count = 0
using sequential pattern ....
transfer bytes [512]
0000: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
0010: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
0020: 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
0030: 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
0040: 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
0050: 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
0060: 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F
0070: 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
0080: 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
0090: 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
00A0: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF
00B0: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
00C0: C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF
00D0: D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
00E0: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF
00F0: F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE 00
0100: 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
0110: 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
0120: 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
0130: 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40
0140: 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
0150: 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60
0160: 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70
0170: 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80
0180: 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90
0190: 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0
01A0: A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0
01B0: B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0
01C0: C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0
01D0: D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0
01E0: E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0
01F0: F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE 00 01

Now spi0.0 's pinmux is below

pinmux.0x0c302048 = 0x00000400; # spi2_sck_pcc0: spi2, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0c302050 = 0x00000450; # spi2_miso_pcc1: spi2, tristate-enable, input-enable, io_high_voltage-disable, lpdr-disable
pinmux.0x0c302028 = 0x00000400; # spi2_mosi_pcc2: spi2, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0c302038 = 0x00000400; # spi2_cs0_pcc3: spi2, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable

should i change it to the below version?

pinmux.0x0243d040 = 0x00000450; # spi1_sck_pz3: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d020 = 0x00000450; # spi1_miso_pz4: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d058 = 0x00000450; # spi1_miso_pz4: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d010 = 0x00000448; # spi1_cs0_pz6: rsvd1, pull-up, tristate-disable, input-enable, lpdr-disable
pinmux.0x0243d010 = 0x00000448; # spi1_cs0_pz6: rsvd1, pull-up, tristate-disable, input-enable, lpdr-disable

Below is NX setting. On Xavier NX spi1(spidev0.0) is master mode and spi3(spidev2.0) is slave mode.

Bank: 0 Reg: 0x0243d010 Val: 0x00000448 -> spi1_cs0_pz6
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 -> spi1_miso_pz4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 -> spi1_sck_pz3
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 -> spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 -> spi1_mosi_pz5
nvidia@nvidia-desktop:~$ sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi3
Bank: 0 Reg: 0x0243d008 Val: 0x00000444 -> spi3_miso_py1
Bank: 0 Reg: 0x0243d018 Val: 0x00000448 -> spi3_cs0_py3
Bank: 0 Reg: 0x0243d028 Val: 0x00000448 -> spi3_cs1_py4
Bank: 0 Reg: 0x0243d048 Val: 0x00000444 -> spi3_sck_py0
Bank: 0 Reg: 0x0243d060 Val: 0x00000444 -> spi3_mosi_py2

Hi ShaneCCC
My board is AGX Xavier. So please give me your advice about AGX Xavier pinmux setting.
Thank you very much.

Just configure the spix_[miso/mosi/sck]_xx as 0x00000444 and spix_csx_xxx as 0x00000448 to try.

1: Your suggestion is setting the SPI1 and SPI3 loopback mode?
2: Now i use the FPGA make the SPI1 Pin send singnal direct to the SPI2 pin for test, what’s the pinmux setting for this.
3: Would you give me the spidev_test.c code

  1. No, just any of SPI connect loopback with SPI2, due to you want to have SPI2 as slave.
  2. Don’t understand this. Should be FPGA connect to SPI2 why involve SPI1?
  3. You can get the source code from public, Sorry can public this with internal modification.

Hi ShaneCCC
now i am confused of the information you give me, so i want to make it clear and ask you some questions.
1: Whatever the SPI pin mode is master or slave, what’s the setting of SPI pinmux, is it part1 or part2? which is useful?

#part1
pinmux.0x0243d040 = 0x00000450; # spi1_sck_pz3: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d020 = 0x00000450; # spi1_miso_pz4: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d058 = 0x00000450; # spi1_miso_pz4: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d010 = 0x00000448; # spi1_cs0_pz6: rsvd1, pull-up, tristate-disable, input-enable, lpdr-disable
pinmux.0x0243d010 = 0x00000448; # spi1_cs0_pz6: rsvd1, pull-up, tristate-disable, input-enable, lpdr-disable

#part2
#Just configure the spix_[miso/mosi/sck]_xx as 0x00000444 and spix_csx_xxx as 0x00000448
Bank: 0 Reg: 0x0243d010 Val: 0x00000448 -> spi1_cs0_pz6
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 -> spi1_miso_pz4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 -> spi1_sck_pz3
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 -> spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 -> spi1_mosi_pz5

2: Is the setting like below just useful for loopback test?

#part2
#Just configure the spix_[miso/mosi/sck]_xx as 0x00000444 and spix_csx_xxx as 0x00000448
Bank: 0 Reg: 0x0243d010 Val: 0x00000448 -> spi1_cs0_pz6
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 -> spi1_miso_pz4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 -> spi1_sck_pz3
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 -> spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 -> spi1_mosi_pz5

3: I want to make a loopback test, which SPI group doesn’t need any hardware connection can be seted to test? for ex. SPI1 and SPI3, are they ?

Thank you for your patient answer.

Best wishes!

  1. Please apply part2
  2. No, it configure as SPI enable. Loopback test only verify if SPI function working or not.
  3. Just need two SPI to connect like below for example SPI1 and SPI3 for loopback test.

SPI1_MOSI<- ->SPI3_MOSI, SPI1_MISO<- ->SPI3_MISO, SPI1_CLK<–>SPI3_CLK, SP1_CS0 <–> SPI3_CS0 and SPI1_CS1->SPI3_CS1.