Modified `panel-a-wxga-8-0.dtsi1
/*
* arch/arm/boot/dts/panel-a-wxga-8-0.dtsi
*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <dt-bindings/display/tegra-dc.h>
#include <dt-bindings/display/tegra-panel.h>
/ {
host1x {
dsi {
panel_a_wxga_8_0: panel-a-wxga-8-0 {
status = "disabled";
compatible = "a,wxga-8-0";
nvidia,dsi-instance = <DSI_INSTANCE_0>;
nvidia,dsi-n-data-lanes = <2>;
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
nvidia,dsi-refresh-rate = <60>;
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;
nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>;
nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
/*
nvidia,dsi-init-cmd = <TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_GENERIC_LONG_WRITE 0x3 0x0 0x0 0xf0 0x5a 0x5a 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 5>,
<TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0 CMD_NOT_CLUBBED>,
<TEGRA_DSI_DELAY_MS 5>,
<TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0 CMD_NOT_CLUBBED>,
<TEGRA_DSI_DELAY_MS 10>,
<TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD DSI_GENERIC_LONG_WRITE 0x4 0x0 0x0 0xc3 0x40 0x00 0x28 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 170>;
*/
nvidia,dsi-init-cmd = <TEGRA_DSI_DELAY_MS 10>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE1 0x93 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE2 0x65 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE3 0xF8 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x80 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x01 0x3C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x03 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x04 0x3C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0C 0x74 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x17 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x18 0xF7 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x19 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1A 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1B 0xF7 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1C 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x24 0xF1 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0x23 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x37 0x09 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x38 0x04 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x39 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3A 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3C 0x70 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3D 0xFF 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3E 0xFF 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3F 0x7F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x40 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x41 0xA0 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x43 0x1E 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x44 0x0B 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x45 0x28 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x55 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x57 0xA9 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x59 0x0A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5A 0x2D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5B 0x1A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5C 0x15 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5D 0x7F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5E 0x69 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5F 0x59 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x60 0x4C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x61 0x47 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x62 0x38 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x63 0x3D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x64 0x27 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x65 0x41 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x66 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x67 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x68 0x5B 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x69 0x46 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6A 0x49 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6B 0x3A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6C 0x34 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6D 0x25 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6E 0x15 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6F 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x70 0x7F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x71 0x69 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x72 0x59 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x73 0x4C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x74 0x47 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x75 0x38 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x76 0x3D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x77 0x27 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x78 0x41 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x79 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7A 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7B 0x5B 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7C 0x46 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7D 0x49 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7E 0x3A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x7F 0x34 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x80 0x25 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x81 0x15 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x82 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x02 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x00 0x50 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x01 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x02 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x03 0x52 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x04 0x77 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x05 0x57 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x06 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x07 0x4E 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x08 0x4C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x09 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0A 0x4A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0B 0x48 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0C 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0D 0x46 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0E 0x44 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0F 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x10 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x11 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x12 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x13 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x14 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x15 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x16 0x51 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x17 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x18 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x19 0x53 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1A 0x77 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1B 0x57 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1C 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1D 0x4F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1E 0x4D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x1F 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x20 0x4B 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x21 0x49 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x22 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x23 0x47 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x24 0x45 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x25 0x41 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x26 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x27 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x28 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x29 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2A 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2B 0x5F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2C 0x01 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2D 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2E 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2F 0x13 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x30 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x31 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x32 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x33 0x0D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x34 0x0F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x36 0x05 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x37 0x07 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x38 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x39 0x09 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3A 0x0B 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3B 0x11 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3C 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3D 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3E 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3F 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x40 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x41 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x42 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x43 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x44 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x45 0x12 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x46 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x47 0x17 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x48 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x49 0x0C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4A 0x0E 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4B 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4C 0x04 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4D 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4E 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x4F 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x50 0x0A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x51 0x10 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x52 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x53 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x54 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x55 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x56 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x57 0x1F 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x58 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5B 0x10 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5C 0x06 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5D 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5E 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x5F 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x60 0x40 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x61 0x03 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x62 0x04 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x63 0x6C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x64 0x6C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x65 0x75 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x66 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x67 0xB4 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x68 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x69 0x6C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6A 0x6C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6B 0x0C 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6D 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6E 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x6F 0x88 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x75 0xBB 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x76 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x77 0x05 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x78 0x2A 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x04 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x09 0x11 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x0E 0x48 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2B 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2D 0x03 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x2E 0x03 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xE0 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x11 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 120>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x29 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 5>;
nvidia,dsi-n-init-cmd = <202>;
disp-default-out {
nvidia,out-type = <TEGRA_DC_OUT_DSI>;
nvidia,out-width = <107>;
nvidia,out-height = <172>;
nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
nvidia,out-parent-clk = "pll_d_out0";
nvidia,out-xres = <800>;
nvidia,out-yres = <1280>;
};
display-timings {
800x1280-32 {
clock-frequency = <74880000>;
hactive = <800>;
vactive = <1280>;
hfront-porch = <20>;
hback-porch = <20>;
hsync-len = <20>;
vfront-porch = <30>;
vback-porch = <8>;
vsync-len = <4>;
nvidia,h-ref-to-sync = <4>;
nvidia,v-ref-to-sync = <1>;
};
};
cmu {
nvidia,cmu-csc = < 0x138 0x3ba 0x00d
0x3f5 0x120 0x3e6
0x3fe 0x3f8 0x0e9 >;
nvidia,cmu-lut2 = < 0 1 2 3 4 5 6 6
7 8 9 10 11 11 12 13
13 14 15 15 16 17 17 18
18 19 19 20 20 21 21 22
22 23 23 23 24 24 24 25
25 25 26 26 26 27 27 27
28 28 28 28 29 29 29 29
30 30 30 30 31 31 31 31
32 32 32 32 33 33 33 33
34 34 34 35 35 35 35 36
36 36 37 37 37 37 38 38
38 39 39 39 39 40 40 40
41 41 41 41 42 42 42 43
43 43 43 44 44 44 45 45
45 45 46 46 46 46 47 47
47 47 48 48 48 48 49 49
49 49 50 50 50 50 50 51
51 51 51 52 52 52 52 52
53 53 53 53 53 53 54 54
54 54 54 55 55 55 55 55
55 56 56 56 56 56 56 57
57 57 57 57 57 57 58 58
58 58 58 58 59 59 59 59
59 59 59 60 60 60 60 60
60 60 61 61 61 61 61 61
61 62 62 62 62 62 62 62
63 63 63 63 63 63 63 64
64 64 64 64 64 64 65 65
65 65 65 65 66 66 66 66
66 66 66 67 67 67 67 67
67 68 68 68 68 68 68 69
69 69 69 69 69 70 70 70
70 70 70 71 71 71 71 71
71 72 72 72 72 72 72 73
73 73 73 73 73 74 74 74
74 74 74 74 75 75 75 75
75 75 76 76 76 76 76 76
77 77 77 77 77 77 77 78
78 78 78 78 78 79 79 79
79 79 79 79 80 80 80 80
80 80 80 80 81 81 81 81
81 81 81 82 82 82 82 82
82 82 82 83 83 83 83 83
83 83 83 83 84 84 84 84
84 84 84 84 85 85 85 85
85 85 85 85 85 85 86 86
86 86 86 86 86 86 86 86
87 87 87 87 87 87 87 87
87 87 88 88 88 88 88 88
88 88 88 88 88 88 89 89
89 89 89 89 89 89 89 89
89 89 90 90 90 90 90 90
90 90 90 90 90 90 91 91
91 91 91 91 91 91 91 91
91 91 91 92 92 92 92 92
92 92 92 92 92 92 92 92
93 93 93 93 93 93 93 93
93 93 93 93 93 93 94 94
94 94 94 94 94 94 94 94
94 94 94 94 95 95 95 95
95 95 95 95 95 95 95 95
95 96 96 96 96 96 96 96
96 96 96 96 96 96 97 97
97 97 97 97 97 97 97 97
98 99 99 100 101 101 102 103
103 104 105 105 106 107 107 108
109 110 110 111 112 112 113 114
114 115 115 116 117 117 118 119
119 120 120 121 121 122 123 123
124 124 125 125 126 126 127 128
128 129 129 130 130 131 131 132
132 133 133 134 134 135 135 136
136 137 138 138 139 139 140 140
141 141 142 142 143 143 144 144
144 145 145 146 146 147 147 148
148 149 149 150 150 151 151 152
152 153 153 153 154 154 155 155
156 156 157 157 157 158 158 159
159 160 160 160 161 161 162 162
162 163 163 164 164 164 165 165
165 166 166 167 167 167 168 168
168 169 169 169 170 170 171 171
171 172 172 172 173 173 173 174
174 174 175 175 175 176 176 176
177 177 177 178 178 178 179 179
179 180 180 180 181 181 181 182
182 182 183 183 183 184 184 184
185 185 185 185 186 186 186 187
187 187 188 188 188 189 189 189
190 190 190 191 191 191 191 192
192 192 193 193 193 194 194 194
195 195 195 195 196 196 196 197
197 197 198 198 198 199 199 199
199 200 200 200 201 201 201 202
202 202 203 203 203 203 204 204
204 205 205 205 206 206 206 207
207 207 208 208 208 208 209 209
209 210 210 210 211 211 211 212
212 212 213 213 213 214 214 214
215 215 215 215 216 216 216 217
217 217 218 218 218 219 219 219
220 220 220 220 221 221 221 222
222 222 222 223 223 223 224 224
224 224 225 225 225 226 226 226
226 227 227 227 227 228 228 228
229 229 229 229 230 230 230 230
230 231 231 231 231 232 232 232
232 233 233 233 233 234 234 234
234 234 235 235 235 235 236 236
236 236 236 237 237 237 237 238
238 238 238 238 239 239 239 239
239 240 240 240 240 240 241 241
241 241 241 242 242 242 242 243
243 243 243 243 244 244 244 244
244 245 245 245 245 245 246 246
246 246 246 247 247 247 247 248
248 248 248 248 249 249 249 249
250 250 250 250 251 251 251 251
251 252 252 252 253 253 253 253
254 254 254 254 255 255 255 255 >;
};
};
};
};
backlight {
panel_a_wxga_8_0_bl: panel-a-wxga-8-0-bl {
status = "disabled";
compatible = "a,wxga-8-0-bl";
pwms = <&tegra_pwm 1 1000000>;
max-brightness = <255>;
default-brightness = <224>;
bl-measured = < 0 0 1 2 3 4 5 6
7 8 9 9 10 11 12 13
13 14 15 16 17 17 18 19
20 21 22 22 23 24 25 26
27 27 28 29 30 31 32 32
33 34 35 36 37 37 38 39
40 41 42 42 43 44 45 46
47 48 48 49 50 51 52 53
54 55 56 57 57 58 59 60
61 62 63 64 65 66 67 68
69 70 71 71 72 73 74 75
76 77 77 78 79 80 81 82
83 84 85 87 88 89 90 91
92 93 94 95 96 97 98 99
100 101 102 103 104 105 106 107
108 109 110 111 112 113 115 116
117 118 119 120 121 122 123 124
125 126 127 128 129 130 131 132
133 134 135 136 137 138 139 141
142 143 144 146 147 148 149 151
152 153 154 155 156 157 158 158
159 160 161 162 163 165 166 167
168 169 170 171 172 173 174 176
177 178 179 180 182 183 184 185
186 187 188 189 190 191 192 194
195 196 197 198 199 200 201 202
203 204 205 206 207 208 209 210
211 212 213 214 215 216 217 219
220 221 222 224 225 226 227 229
230 231 232 233 234 235 236 238
239 240 241 242 243 244 245 246
247 248 249 250 251 252 253 255 >;
};
};
};