how to enable the combination of "pcie x4 + pcie x1" in TK1

hi all~

in a previous post:

Jachen ever mentioned that

in /boot/extlinux/extlinux.conf

if we set the value of ‘lane_owner_info’ to 1 (originally it was 6)

then, the PCIE lane ownership would be configured as PCIe x4_x1 after a reboot.

In my customized board:

PCIE Controller-1 is connected as follows:

PEX_CLK1P/N            --------->       FPGA.PCIE-CORE.CLKP/N

PEX_L0_RST_N           --------->       FPGA.PCIE-CORE.RST_N

PEX_L0_CLK_REQ_N       <---------       tied logic low (1'b0)

PEX_TX4P/N             --------->       FPGA.PCIE_RXP/N [0]
PEX_TX3P/N             --------->       FPGA.PCIE_RXP/N [1]   
PEX_TX2P/N             --------->       FPGA.PCIE_RXP/N [2]
PEX_USB3_TX1P/N        --------->       FPGA.PCIE_RXP/N [3]

PEX_RX4P/N             <---------       FPGA.PCIE_TXP/N [0]
PEX_RX3P/N             <---------       FPGA.PCIE_TXP/N [1]
PEX_RX2P/N             <---------       FPGA.PCIE_TXP/N [2]
PEX_USB3_RX1P/N        <---------       FPGA.PCIE_TXP/N [3]

PCIE Controller-2 is connected as follows:

PEX_CLK2P/N            --------->       RTL8111GS(ETH-PHY).CLKP/N

PEX_L1_RST_N           --------->       RTL8111GS(ETH-PHY).RST_N

PEX_L1_CLK_REQ_N       <---------       RTL8111GS(ETH-PHY).CLK_REQ_N

USB3_TX0P/N            --------->       RTL8111GS(ETH-PHY).HSIP/N
USB3_RX0P/N            <---------       RTL8111GS(ETH-PHY).HSOP/N

            the above connection is made according to the USECASE-3 of

            Table 40. USB 3.0, PCIe & SATA Lane Mapping Use Cases, pp114 of the


            USECASE-3 = pcie_x4_x1 + sata

will the above PCIE lane mapping work (at least “lspci -vvv” is supposed to
dump some PCIE info about ETH-PHY and FPGA )
by just changing the ‘lane_owner_info’ in /boot/extlinux/extlinux.conf
from 6 to 1 ?

is it all that needs (given the correct hardware connection as shown above in my customized design) ?

Yes. That should be fine and should work