how to enable two USB3.0 ?

Do anyone know how to enable two USB3.0 port?
I am using customer carrier board,i want to enable two USB3.0 port.

  1. F43, F44, C43, C44
    A38, A39, A18

  2. G39, G40, D39, D40
    B37 A17 A36 B40 B39

after try https://elinux.org/Jetson/TX2_USB#USB-Lane_Mapping,
the first one[F43, F44, C43, C44 A38, A39, A18] work well,but the second one can not work.

I make some modification as following.

  1. modify the ODMDATA value in file “p2771-0000.conf.common”
process_board_version()
    {
        local kerndtbfab="-c03";                    # default = C03
        ODMDATA=0x6090000;  # default = C0X
  1. comment out above three fragment in hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-plugin-manager/
    tegra186-quill-p3310-1000-a00-plugin-manager.dtsi
/****************************************************************
		fragment-500-pcie-config {
			ids = ">=3310-1000-500";
			override@0 {
				target = <&tegra_pcie>;
				_overlay_ {
					pci@1,0 {
						nvidia,num-lanes = <4>;
					};
					pci@2,0 {
						nvidia,num-lanes = <0>;
					};
					pci@3,0 {
						nvidia,num-lanes = <1>;
					};
				};
			};
		};
		****************************************************************/
 
		/***************************************************************
		fragment-500-xusb-config {
			ids = ">=3310-1000-500";
			override@0 {
				target = <&{/xhci@3530000}>;
				_overlay_ {
					phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
						<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
						<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
						<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
					phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-0";
				};
			};
			override@1 {
				target = <&tegra_xusb_padctl_pinmux_default>;
				_overlay_ {
					usb3-std-A-port2 {
						nvidia,lanes = "usb3-0";
					};
					e3325-usb3-std-A-HS {
						status = "okay";
					};
				};
			};
		};
		************************************************************/
 
		/*****************************************
		fragment-500-e3325-pcie {
			enable-override-on-all-matches;
			ids = ">=3310-1000-500";
			odm-data = "enable-pcie-on-uphy-lane0";
			override@0 {
				target = <&{/xhci@3530000}>;
				_overlay_ {
					phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
						<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
						<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>;
					phy-names = "utmi-0", "utmi-1", "utmi-2";
				};
			};
			override@1 {
				target = <&tegra_xusb_padctl_pinmux_default>;
				_overlay_ {
					usb3-std-A-port2 {
						status = "disabled";
					};
				};
			};
 
			override@2 {
				target = <&tegra_main_gpio>;
				_overlay_ {
					pcie0_lane2_mux {
						status = "okay";
					};
				};
			};
		};
		*********************************************************/
  1. modify the file hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi to change vbus-2-supply from vdd_usb2_5v to battery_reg
pinctrl@3520000 {
     vbus-0-supply = <&vdd_usb0_5v>; 
     vbus-1-supply = <&vdd_usb1_5v>;
        vbus-2-supply = <&battery_reg>; 
     vbus-3-supply = <&battery_reg>; 
     vddio-hsic-supply = <&battery_reg>;
     avdd_usb-supply = <&spmic_sd3>;
     vclamp_usb-supply = <&spmic_sd2>;
     avdd_pll_erefeut-supply = <&spmic_sd2>;
  };
  1. modify the file hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts
gpio@2200000 {
		sdmmc-wake-support-input {
			status = "okay";
		};

		sdmmc-wake-support-output {
			status = "okay";
		};
		pcie0_lane2_mux {
			status = "okay"; //This is for switch from usb3.0 to x1 PCIe  on M.2.
		};
	};

pcie-controller@10003000 {
		pci@1,0 {
			nvidia,num-lanes = <2>;
			nvidia,disable-clock-request;
			status = "okay";
		};
		pci@2,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
		pci@3,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
	};

xhci@3530000 {
		phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(2)>;
		phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-1", "usb3-2";
};

pinctrl@3520000 {
	    pinmux {
		usb3-std-A-port2 {
			nvidia,lanes = "usb3-1";
			nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
			status = "okay";
		};
		usb3-std-A-port3 {
			nvidia,lanes = "usb3-2";
			nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
			status = "okay";
		};
		e3325-usb3-std-A-HS {
                    status = "okay"; //This is usb2.0 port on M.2
		};
		};
};

Are there any wrong step, many thanks?

usb3_0.png
usb3_1.png

Hi,
You have to check adaptation guide and modify device tree according to your hardware USB lane mapping.

Please also refer to debug tips at
https://devtalk.nvidia.com/default/topic/1048285/jetson-tx2/how-to-setup-usb-config-4-for-tx2-l4t-28-2-1-/post/5320806/#5320806

1 Like

i refer to “l4t-driver-package-tx2-adaptation-guide”, chapter “USB Lane Mapping”.
According to my carrier board design, PCie interface configuration shouled be #6,
so i need to modify the ODMDATA to a different value ?

#1 ODMDATA 0x90000
#2 ODMDATA 0x1090000
#3 ODMDATA 0x6090000

For configuration #6, ODMDATA value ? how is the ODMDATA defined ?

For PCie interface configuration #6, ODMDATA should be 0x3090000,right?

Yes. Please modify the value in p2771-0000.conf.common.

Thank you very much. Two USB3.0 port is working well now.