Image Desynchronization Issue in DOL2 Mode

[William_chen]

Hello everyone,

I’m currently facing an issue while debugging DOL2 simulation. The problem I’m encountering is that the images are not synchronized properly, leading to image splitting as shown in the image below:

• I captured this RAW：
  DOL2_100-1.nvraw (8.1 MB)
• trace log：
  tracelog.txt (60.1 KB)

I have been trying to narrow down the root cause of this problem, but I’m hitting a roadblock. Could anyone kindly provide some insights into what might be causing this issue? Here’s some context about my setup and what I’ve already checked:

dts：

mode5 { /*  */
					mclk_khz = "24000";
					num_lanes = "4";
					tegra_sinterface = "serial_c";
					phy_mode = "DPHY";
					discontinuous_clk = "no";
					dpcm_enable = "false";
					cil_settletime = "0";
					lane_polarity = "0";

					active_w = "1944";		//1920+8+8+8
					active_h = "2356";		//(H3+H4+H5+H6+H7+H8+VBP)*2=(10+10+4+58+8+1080+8)*2
					mode_type = "bayer_wdr_dol";
					pixel_phase = "rggb";
					csi_pixel_bit_depth = "10";
					dynamic_pixel_bit_depth = "10";
					readout_orientation = "0";
					line_length = "1944";
					inherent_gain = "1";
					mclk_multiplier = "12";
					pix_clk_hz = "288000000";

					gain_factor = "1000";
					min_gain_val = "1"; 		/* 0 dB */
					max_gain_val = "72000"; /* dB */
					step_gain_val = "300"; /* 0.3 */
					default_gain = "1";
					min_hdr_ratio = "32";
					max_hdr_ratio = "32";
					framerate_factor = "1000000";
					min_framerate = "30000000";
					max_framerate = "30000000";
					step_framerate = "1";
					default_framerate = "30000000";
					exposure_factor = "1000000";
					min_exp_time = "26"; /*us, 2 lines*/
					max_exp_time = "30000";
					step_exp_time = "1";
					default_exp_time = "30000";/* us */
					embedded_metadata_height = "1";
					
					/* WDR related settings */
					num_of_exposure = "2";
					num_of_ignored_lines = "24"; 
					num_of_lines_offset_0 = "58";
					num_of_ignored_pixels = "8";
					num_of_left_margin_pixels = "8";
					num_of_right_margin_pixels = "8";
					
				};

and,imx622 image drawing of DOL 2 frame.

1、I using Jetson Orin Nano,R35.4.1

2、I increase the pix_clk_hz value, it changes but it doesn’t go away

pix_clk_hz = "288000000"; -->pix_clk_hz = "600000000";

( The split seems to have narrowed)

3、 I increase the clock rate,it changes but it doesn’t go away

echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee  /sys/kernel/debug/bpmp/debug/clk/isp/rate
cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate

The split seems to have narrowed too

4、I’ve tried many times to change active_h and num_of_lines_offset_0, but the problem still persists

5、My sensor(imx662) configuration is no problem, I have been tested on other platforms

Despite these efforts, I haven’t been able to resolve the image desynchronization problem. If anyone has faced a similar issue or has insights to offer, I would greatly appreciate your input.

Thank you

[ShaneCCC]

Does the SDR mode without problem?

[William_chen]

SDR mode is normal, including the previously debugged DOL3 mode is also normal, but because DOL3 can not use nvargus_nvraw to capture raw. So we find SONY has applied for a DOL2 Settings

[ShaneCCC]

What’s the different for DOL3 with DOL2? 3 frames and 2 frames?
Current don’t support virtual channel DOL mode only support the LI(line information) for fusion.

[William_chen]

DOL3 DOL2 and no other difference, just different output frames.

There is a very strange phenomenon, I use DOL3 driver to open the camera, the screen display is normal; After that I manually wrote to the sensor register and changed it to DOL2 output. The picture was still fine.

[ShaneCCC]

If that I would suspect it could be sensor REG configure cause the problem.