Hi NVIDIA Team and Community,
I am currently working on the power and thermal design for a custom carrier board based on the Jetson Thor T5000.
According to the Jetson Thor Series Modules Data Sheet, the Total Module Power (TMP) is rated at 130W. However, for our precise thermal simulation (junction temperature estimation) and power rail design, we need to estimate the power consumption of the SoC die itself, excluding the LPDDR5X, PMIC losses, and other on-module components.
I have checked the public datasheet but couldn’t find a breakdown of the power budget.
Could you provide:
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An estimated power consumption for the SoC logic alone (e.g., VDD_CPU + VDD_GPU + VDD_SOC rails) under the 130W MAXN mode?
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Or, a rough percentage of the TDP that is typically allocated to the SoC silicon? (e.g., is it around 80-85%?)
This data is critical for determining our heatsink requirements for the specific die area.
Thanks in advance for your support!
Please refer to the Jetson Thor Series Thermal Design Guide for thermal solution design guidance and requirements.
Thank you for directing me to the Jetson Thor Series Modules Thermal Design Guide.
I have reviewed the document carefully, specifically Section 1.3.1, which defines the Total Module Power (TMP), and Table 2-1, which outlines the thermal specifications based on the 130W MAXN mode.
However, the TDG treats the module as a single thermal node with a total heat dissipation of 130W. For our custom carrier board design, we are performing a detailed CFD thermal simulation to estimate the Junction Temperature more accurately.
The issue is:
Using the full 130W (TMP) applied solely to the SoC die area in our simulation results in an unrealistically high heat flux density, as this 130W actually includes power dissipated by the LPDDR5X memory, PMICs, and PCB losses—not just the SoC silicon.
Could you please clarify:
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Is there an estimated breakdown of the power budget? (e.g., estimated SoC dynamic power vs. Memory/Uncore power under MAXN load?)
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Or, for thermal simulation purposes, what percentage of the TMP (130W) should be applied specifically to the SoC die junction? (e.g., is 80-85% a safe assumption?)
Best regards
The power breakdown and % of power on the SoC die are both highly dependent on the types of workloads so there is no more specific information than provided in the Thermal Design Guide. Refer to the descriptions for balanced and unbalanced workloads in Table 3-1:
