Hi all，
we have a customized carrier board， in which，
FPGA is in charge of TX2’s powering up…
we have implemented the same power up sequence
as described in the OEM design guide，
however the TX2 module does not boot up
(we have connect a keyboard to the USB3.0
port of our customized carrier board，but
the keyboard does not respond to the
NUM lock press.
note that in the TX2‘s development kit，this is true
)
hence，we infer that，a board config EEPROM may be needed～
is that true？
Hi Phoenixlee,
You mean you judge the module not boot up by keyboard not working? Did you check the log? And already measured the power on sequence following that of OEM DG? EEPROM on carrier board is not must.
Hi，Trumany
right on！
i guess module booting up can be verified
by observing the response from keyboard
to special key，e.g. NUM lock,
1， TX2 module inserted into NVIDIA’s TX2 developer kit
keyboard works fine
it responds to NUM lock press
2， TX2 module inserted into My carrier board:
USB mouse/keyboard will be powered off ！！！
in a few seconds，let alone key press responses～～～
But，i have found a new phenomenon:
once the FPGA Powers up TX2 module，
TX2.UART0 will just behave as 'echo'
i.e.， it will simply bounce your input
for instance，
in secure CRT，(a UART utility run in Windows)
TX2 will not output any log itself
but if you press key 'A'，U will receive character
'A' ，and it will be displayed in secure CRT
now that TX2.UART0 works，
i guess it has already been brought up
but why can’t i see any boot log？
why not keyboard response to NUM lock press？
why does TX2's UART0 only works in "echo"
mode～～～？？？
please help me with this～～
thanks～
About FPGA controlling power on sequence… in fact, the only thing FPGA need to do is to control the onkey pressing, there should be some difference between your board and dev kit carrier board, which might hold the system. Can you measure the power up sequence first as the Figure 3 of OEM DG showing? So as to confirm no signal violates the sequence.
[i] 2， TX2 module inserted into My carrier board:
USB mouse/keyboard will be powered off ！！！
in a few seconds，let alone key press responses～～～
But，i have found a new phenomenon:
once the FPGA Powers up TX2 module，
TX2.UART0 will just behave as 'echo'[/i]
Hello, when I refer to the logic diagram, I find nv_res,nv_cap. What do you mean
Hi, please describe more detail, what do you mean the logic diagram? Where did you find nv_res, nv_cap? Which doc are you talking about?
I’m doing hardware logic design,
When referring to the logical design of TX2,
There are some resistors and capacitors in it, marked with nv_res and nv_cap,
Jetson_TX1_TX2_Developer_Kit_Carrier_Board_Design_Files_C02.zip,
File: P2597_C02_OrCAD_schematics. PDF
hi
On page 19, the top of C235 is marked with nv_cap.
Nv_res, nv_cap are the signal_model name of the symbols, they will be shown in sch if this attribute is set to visible. You can skip these marks.
Thank you for your reply from Trumany！