Is PHY IC 88E1512-A0-NNP2I000 for 1G supported on AGX Orin Industrial

nagesh_accord · February 25, 2026, 4:26am

Hi,
Please let us know if Marvell PHY IC 88E1512-A0-NNP2I000 for 1G is supported on AGX Orin Industrial.

thanks,
Nagesh R

carolyuu · February 25, 2026, 4:48am

*** Please note that this reply is generated by LLM automatically ***

The provided context does not explicitly mention the support for Marvell PHY IC 88E1512A0NNP2I000 on Jetson AGX Orin Industrial. However, I can provide some general information about the Jetson AGX Orin and its compatibility with various components.

The Jetson AGX Orin is a high-performance AI computer module designed for industrial and edge AI applications. It features a powerful NVIDIA Ampere GPU, a multi-core CPU, and a range of interfaces for connecting peripherals and sensors.

Regarding the Marvell PHY IC 88E1512A0NNP2I000, it is a 1G Ethernet PHY (Physical Layer) transceiver chip that supports IEEE 802.3u 1000BASE-T and 100BASE-TX standards. While the Jetson AGX Orin does support Ethernet connectivity, the specific PHY IC used on the module is not explicitly mentioned in the provided context.

However, the Jetson AGX Orin Developer Kit documentation mentions that the module has a P3701 System on Module (SOM) connected to a P3737 carrier board, and both the SOM and carrier board have an EEPROM where the board ID is saved. The documentation also mentions that the SOM can be used without any software configuration modifications.

To determine if the Marvell PHY IC 88E1512A0NNP2I000 is supported on Jetson AGX Orin Industrial, I would recommend checking the following:

The Jetson AGX Orin Industrial datasheet or documentation to see if it mentions the specific PHY IC used on the module.
The Marvell PHY IC 88E1512A0NNP2I000 datasheet to see if it is compatible with the Jetson AGX Orin’s Ethernet interface.
The Jetson AGX Orin’s software development kit (SDK) documentation to see if it provides any information on configuring or supporting specific PHY ICs.

If you are unable to find the necessary information, I would recommend reaching out to NVIDIA’s technical support or the Jetson forums for further assistance.

In comparison to other Jetson modules, the Jetson AGX Orin is a more recent and powerful module, and its compatibility with various components may differ from older modules like the Jetson Xavier NX or Jetson TX2. However, without more specific information, it is difficult to provide a definitive answer on the support for the Marvell PHY IC 88E1512A0NNP2I000 on Jetson AGX Orin Industrial.

*** Please give the thumbs up if you get answers you like. Or provide feedback to help us improve the answer. ***

ChrisB_NV · February 25, 2026, 11:09pm

That PHY has not been directly validated by NVIDIA but the RGMII is compatible with the AGX Orin Industrial and there are several forum members and others using the 88E1512 with AGX Orin.

Problem with RGMII Ethernet (88E1512) with JP 5.1.0 on AGX Orin (was working with JP 5.0.1DP and on Xavier) - #12 by WayneWWW

We’ve checked this 88E1512 on many other end users/partners already.

nagesh_accord · February 26, 2026, 4:02am

Thanks for the updates.
We understand the Marvell PHY driver for this is already part of Linux forTegra kernel image. Kindly confirm.

WayneWWW · February 27, 2026, 8:26am

Yes, that one is already in the kernel.

nagesh_accord · February 27, 2026, 10:09am

We are getting one error after doing the below changes in device tree for RGMII as per below link:

phy-mode = “rgmii-id”;
phy-handle = <$phy>;
nvidia,phy-reset-gpio = <$tegra_main_gpio TEGRA234_MAIN_GPIO(G, 5) 0>

mdio {
compatible = “nvidia,eqos-mdio”;
#address-cells = <1>;
#size-cells = <0>;
phy: phy@1 {
    reg = <1>;
    nvidia,phy-rst-pdelay-msec = <224>; /* msec */
    nvidia,phy-rst-duration-usec = <10000>; /* usec */
    interrupt-parent = <$tegra_main_gpio>;
    interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
};
};

If we use $tegra_main_gpio, we are getting parse error, so changed to &tegra_main_gpio.
After changing to &tegra_main_gpio, we are getting the above shown phandle_reference errors..

Any idea why?

nagesh_accord · March 2, 2026, 4:56am

One more query:

In the below link they have not mentioned the ethernet node address ( ethernet@xxxxxxxx ) that we should be using for AGX Orin Industrial for 1G

As per the forum search, we found ethernet@2310000 address

but we getting compile error as per my previous post. Kindly let us know how to fix this issue.

Thanks.

KevinFFF · March 2, 2026, 6:50am

If you are using Jetpack 6.x, please specify &gpio instead.

nagesh_accord · March 2, 2026, 9:16am

Thanks.
Now we were now able to build the device tree successfully and did the flashing.

but still 1G onboard ethernet not working. Its out customized carrier board for Jetson AGX Orin Industrail - r36.4.3 version.

Pls find the attached

bootlog, running device tree and dmesg attached for your reference.

Pls let us know what could be the issue.

Thanks.

running-device-tree-3-mar-1G-not-work.log (396.9 KB)
boot-log-3-mar-1g-not-wrking.log (104.3 KB)
ethernet_1G_onboard-notworking-3-mar.log (73.8 KB)

KevinFFF · March 3, 2026, 5:23am

The following log shows that Linux is probing the MDIO bus of 6800000.ethernet but cannot find any PHY at address 0, so the interface fails to come up:

[   14.676526] mdio_bus 6800000.ethernet: MDIO device at address 0 is missing.
[   14.676541] nvethernet 6800000.ethernet: failed to connect PHY
[   14.676546] net eno1: ether_open: Cannot attach to PHY (error: -19)

Could you please confirm the actual MDIO address strapped on the PHY, and make sure it matches both nvidia,mdio_addr and the phy@x { reg = <x>; } node in the device tree?

Also, from the device tree you shared, ethernet@2310000 is currently disabled.
If your 88E1512 RGMII PHY is connected to this MAC (2310000), please enable this node and disable unused MACs (such as ethernet@6800000) to avoid probing MDIO on an interface without a connected PHY.

nagesh_accord · March 3, 2026, 5:54am

KevinFFF:

The following log shows that Linux is probing the MDIO bus of 6800000.ethernet but cannot find any PHY at address 0, so the interface fails to come up:
[   14.676526] mdio_bus 6800000.ethernet: MDIO device at address 0 is missing.
[   14.676541] nvethernet 6800000.ethernet: failed to connect PHY
[   14.676546] net eno1: ether_open: Cannot attach to PHY (error: -19)

This 10G MGBE, which we have kept on hold as of now and not trying. I can disable the status of it in the dts file - tegra234-p3737-0000+p3701-000.dts

In the sample code I saw on forums, I could not find this nvidia,mdio_addr element.
Below is my device tree for onboard ethernet@2310000. here i have enabled the status=okay but not sure why in the device tree log it is showing disabled as told by you.

Ok. I will do this change and do reflashing again and see.

nagesh_accord · March 3, 2026, 12:36pm

@KevinFFF

After updating status=okay in the t234-base-overlay.dts file, I can see that the ethernet@2310000 is enabled.
Is it the right way to do it?
Please find the attached dmesg log, running device tree on jetson and dts files we have updated.
Kindly let us know, what is the issue.
Note: we have updated the PIN muxing also as below.

dmesg-1G-nt-working.log (74.0 KB)
running-dts-3-mar.txt (397.0 KB)

Orin-jetson_agx_orin_industrial-pinmux.txt (65.7 KB)
Orin-jetson_agx_orin_industrial-gpio-default.txt (5.0 KB)
Orin-jetson_agx_orin_industrial-padvoltage-default.txt (2.4 KB)

tegra234-base-overlay.txt (19.7 KB)

tegra234-p3737-0000+p3701-0000.txt (11.6 KB)

Our hardware engineer says the phy address is not known so i have considered it has 0.
Pls check if the RESET, INTERRUPT,RGMMI pins are correctly set.
I think the PINMUX settings for RGMII are not getting reflected in the device tree. Could you confirm. I have updated the change as below as per the documentation provided by Nvidia.

image1299×337 152 KB

Thanks.

nagesh_accord · March 5, 2026, 4:45am

@KevinFFF
Could you pls reply to this query as soon as possible, as we are stuck up and not able to proceed further on with our 1G onboard RGMII based.
Thanks in advance.

KevinFFF · March 5, 2026, 8:52am

Please confirm that your pinmux file is named as pinmux.dtsi and you’ve put it to <Linux_for_Tegra>/bootloader/generic/BCT/.
gpio.dtsi should be put in <Linux_for_Tegra>/bootloader/ and included by pinmux.dtsi.

It should be fine to update the configuration in that device tree. Please just confirm if your configuration is applied correctly after boot up.

nagesh_accord · March 5, 2026, 9:07am

Yes

What I meant was I updated only the status field to “okay” in t234-base-overlay.dts. Rest of changes I have done in tegra234-p3737-0000+p3701-0000.dts
kindly check in the file in previous post attached. The changes I did in tegra234-p3737-0000+p3701-0000.dts are reflecting after bootup except status=okay change, thats the reason I edited t234-base-overlay.dts and after this change “status=okay” for updated after bootup.

One more thing I observe is the below PINXMUXED changes EQOS RGMII TX /RX side changes are not getting updated in the running device tree. Why?

eqos_txc_pe0 {
nvidia,pins = “eqos_txc_pe0”;
nvidia,function = “eqos”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};

  	eqos_td0_pe1 {
  		nvidia,pins = "eqos_td0_pe1";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_DISABLE>;
  		nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  	};

  	eqos_td1_pe2 {
  		nvidia,pins = "eqos_td1_pe2";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_DISABLE>;
  		nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  	};

  	eqos_td2_pe3 {
  		nvidia,pins = "eqos_td2_pe3";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_DISABLE>;
  		nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  	};

  	eqos_td3_pe4 {
  		nvidia,pins = "eqos_td3_pe4";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_DISABLE>;
  		nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  	};

  	eqos_tx_ctl_pe5 {
  		nvidia,pins = "eqos_tx_ctl_pe5";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_DISABLE>;
  		nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  	};

  	eqos_rd0_pe6 {
  		nvidia,pins = "eqos_rd0_pe6";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_ENABLE>;
  		nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  	};

  	eqos_rd1_pe7 {
  		nvidia,pins = "eqos_rd1_pe7";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_ENABLE>;
  		nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  	};

  	eqos_rd2_pf0 {
  		nvidia,pins = "eqos_rd2_pf0";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_ENABLE>;
  		nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  	};

  	eqos_rd3_pf1 {
  		nvidia,pins = "eqos_rd3_pf1";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_ENABLE>;
  		nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  	};

  	eqos_rx_ctl_pf2 {
  		nvidia,pins = "eqos_rx_ctl_pf2";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_ENABLE>;
  		nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  	};

  	eqos_rxc_pf3 {
  		nvidia,pins = "eqos_rxc_pf3";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_ENABLE>;
  		nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  	};

  	eqos_sma_mdio_pf4 {
  		nvidia,pins = "eqos_sma_mdio_pf4";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_DISABLE>;
  		nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  	};

  	eqos_sma_mdc_pf5 {
  		nvidia,pins = "eqos_sma_mdc_pf5";
  		nvidia,function = "eqos";
  		nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  		nvidia,tristate = <TEGRA_PIN_DISABLE>;
  		nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  	};

Also what is the difference between /boot/dtb/kernel-tegra234-p3737-0000+p3701-0008-nv.dtb and /proc/device-tree
Also In the jetson-agx-orin-devkit-industrial.conf, I see BPFDTB_FILE=“tegra234-bpmp-3701-0008-3737-0000.dtb”
how come this is different from the DTB_FILE=“tegra-p3737-0000+p3701-0008-nv.dtb”

Is this causing any discrepancies

Thanks

BigDon · March 5, 2026, 9:34pm

This is what we got the 1GbE going with. Note: the webtool mangled the comments.

JP 6.0 tegra234-p3737-0000+p3701-0000.dts

ethernet@2310000 {
	status = "okay";
	nvidia,mac-addr-idx = <1>;
	nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;
	nvidia,max-platfrom-mtu = <8000>; /\* DER added \*/
	nvidia,pause_frames = <0>;  /\* DER added 0=enable, 1=disable \*/
	phy-mode = "rgmii-id";
	phy-handle = <&phy>;
	nvidia,if-name = "eqos0";
	

	mdio {
		compatible = "nvidia,eqos-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		phy: phy@0 {
			reg = <0>; /\* DER 071823 changed from reg = <1>; \*/
			nvidia,phy-rst-pdelay-msec = <224>; /\* msec \*/
			nvidia,phy-rst-duration-usec = <10000>; /\* usec \*/
			interrupt-parent = <&gpio>;
			interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
			marvell,copper-mode; /\* DER Taken from Xavier \*/
					/\* DER Taken from Xavier - Setup LED\[2\] as interrupt pin (active low) \*/
			marvell,reg-init = <0x03 0x12 0x7fff 0x880>;
		};
	};
};

BigDon · March 5, 2026, 9:44pm

		eqos_txc_pe0 {
			nvidia,pins = "eqos_txc_pe0";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		eqos_td0_pe1 {
			nvidia,pins = "eqos_td0_pe1";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		eqos_td1_pe2 {
			nvidia,pins = "eqos_td1_pe2";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		eqos_td2_pe3 {
			nvidia,pins = "eqos_td2_pe3";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		eqos_td3_pe4 {
			nvidia,pins = "eqos_td3_pe4";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		eqos_tx_ctl_pe5 {
			nvidia,pins = "eqos_tx_ctl_pe5";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		eqos_rd0_pe6 {
			nvidia,pins = "eqos_rd0_pe6";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rd1_pe7 {
			nvidia,pins = "eqos_rd1_pe7";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rd2_pf0 {
			nvidia,pins = "eqos_rd2_pf0";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rd3_pf1 {
			nvidia,pins = "eqos_rd3_pf1";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rx_ctl_pf2 {
			nvidia,pins = "eqos_rx_ctl_pf2";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_rxc_pf3 {
			nvidia,pins = "eqos_rxc_pf3";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_sma_mdio_pf4 {
			nvidia,pins = "eqos_sma_mdio_pf4";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		eqos_sma_mdc_pf5 {
			nvidia,pins = "eqos_sma_mdc_pf5";
			nvidia,function = "eqos";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

BigDon · March 5, 2026, 9:50pm

		soc_gpio17_pg4 {
			nvidia,pins = "soc_gpio17_pg4";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,lpdr = <TEGRA_PIN_DISABLE>;
		};

		soc_gpio18_pg5 {
			nvidia,pins = "soc_gpio18_pg5";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			nvidia,lpdr = <TEGRA_PIN_DISABLE>;
		};

BigDon · March 5, 2026, 9:59pm

Don’t forget the reset and IRQ

BigDon · March 5, 2026, 10:21pm

Also note that because you are using the industrial orin some files are different. A lot of times the files end in 008 or something similar. This may be why your pinmux changes are not taking.

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Is PHY IC 88E1512-A0-NNP2I000 for 1G supported on AGX Orin Industrial

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